[v2,3/7] starfive-visionfive2: package opensbi firmware

Message ID 20230211092152.949442-4-felix.moessbauer@siemens.com
State Superseded, archived
Headers show
Series Add BSP for StarFiveTech VisionFive2 Risc-V board | expand

Commit Message

MOESSBAUER, Felix Feb. 11, 2023, 9:21 a.m. UTC
This patch adds the opensbi firmware for the starfive visionfive2 board,
based on the official BSP package.

Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
---
 .../files/starfive-visionfive2-rules.tmpl     | 17 ++++++++++
 ...ensbi-starfive-visionfive2_1.2+20230107.bb | 31 +++++++++++++++++++
 2 files changed, 48 insertions(+)
 create mode 100644 meta-isar/recipes-bsp/opensbi/files/starfive-visionfive2-rules.tmpl
 create mode 100644 meta-isar/recipes-bsp/opensbi/opensbi-starfive-visionfive2_1.2+20230107.bb

Comments

MOESSBAUER, Felix Feb. 13, 2023, 6:39 a.m. UTC | #1
On Sat, 2023-02-11 at 09:21 +0000, Felix Moessbauer wrote:
> This patch adds the opensbi firmware for the starfive visionfive2
> board,
> based on the official BSP package.
> 
> Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
> ---
>  .../files/starfive-visionfive2-rules.tmpl     | 17 ++++++++++
>  ...ensbi-starfive-visionfive2_1.2+20230107.bb | 31
> +++++++++++++++++++
>  2 files changed, 48 insertions(+)
>  create mode 100644 meta-isar/recipes-bsp/opensbi/files/starfive-
> visionfive2-rules.tmpl
>  create mode 100644 meta-isar/recipes-bsp/opensbi/opensbi-starfive-
> visionfive2_1.2+20230107.bb
> 
> diff --git a/meta-isar/recipes-bsp/opensbi/files/starfive-
> visionfive2-rules.tmpl b/meta-isar/recipes-
> bsp/opensbi/files/starfive-visionfive2-rules.tmpl
> new file mode 100644
> index 00000000..5f35c1c2
> --- /dev/null
> +++ b/meta-isar/recipes-bsp/opensbi/files/starfive-visionfive2-
> rules.tmpl
> @@ -0,0 +1,17 @@
> +#!/usr/bin/make -f
> +
> +ifneq ($(DEB_BUILD_GNU_TYPE),$(DEB_HOST_GNU_TYPE))
> +export CROSS_COMPILE=$(DEB_HOST_GNU_TYPE)-
> +endif
> +
> +UBOOT_DTB_FILE := /usr/share/u-boot/starfive-
> visionfive2/${DTB_UBOOT_JH7110_VF2}
> +FW_TEXT_START := 0x40000000
> +
> +override_dh_auto_build:
> +       CFLAGS= LDFLAGS= $(MAKE) $(PARALLEL_MAKE) PLATFORM=generic \
> +               FW_PAYLOAD_PATH=/usr/lib/u-boot/starfive-
> visionfive2/u-boot.bin \
> +               FW_FDT_PATH=$(UBOOT_DTB_FILE) \
> +               FW_TEXT_START=$(FW_TEXT_START)
> +
> +%:
> +       dh $@
> diff --git a/meta-isar/recipes-bsp/opensbi/opensbi-starfive-
> visionfive2_1.2+20230107.bb b/meta-isar/recipes-bsp/opensbi/opensbi-
> starfive-visionfive2_1.2+20230107.bb
> new file mode 100644
> index 00000000..e7d767c9
> --- /dev/null
> +++ b/meta-isar/recipes-bsp/opensbi/opensbi-starfive-
> visionfive2_1.2+20230107.bb
> @@ -0,0 +1,31 @@
> +#
> +# Copyright (c) Siemens AG, 2023
> +#
> +# SPDX-License-Identifier: MIT
> +
> +inherit dpkg
> +
> +DESCRIPTION = "OpenSBI firmware for StarFive VisionFive 2"
> +
> +SRC_URI = " \
> +    git://github.com/riscv-software-
> src/opensbi.git;destsuffix=opensbi-${PV};protocol=https;branch=master
> \
> +    file://starfive-visionfive2-rules.tmpl"
> +# required patches are not yet part of a release, but will be in 1.3
> +SRCREV = "c8ea836ee33eb778f48f780412e147386dac5301"

Recently more things got integrated into the upstream OpenSBI.
The latest SHA1 is 65c2190b47b14341dac9f763fed2d4ecbbff2a69.

Will update it in a v3, but for now, please manually update that
revision in the bb recipe when testing.

Felix

> +
> +S = "${WORKDIR}/opensbi-${PV}"
> +TEMPLATE_FILES += "starfive-visionfive2-rules.tmpl"
> +TEMPLATE_VARS += "DTB_UBOOT_JH7110_VF2"
> +
> +DEPENDS = "u-boot-starfive-visionfive2"
> +DEBIAN_BUILD_DEPENDS = " \
> +    u-boot-starfive-visionfive2, \
> +    u-boot-starfive-visionfive2-dev"
> +
> +do_prepare_build[cleandirs] += "${S}/debian"
> +do_prepare_build() {
> +    cp ${WORKDIR}/starfive-visionfive2-rules ${WORKDIR}/rules
> +    deb_debianize
> +
> +    echo "build/platform/generic/firmware/fw_payload.bin
> /usr/lib/opensbi/starfive-visionfive2/" > ${S}/debian/install
> +}

Patch

diff --git a/meta-isar/recipes-bsp/opensbi/files/starfive-visionfive2-rules.tmpl b/meta-isar/recipes-bsp/opensbi/files/starfive-visionfive2-rules.tmpl
new file mode 100644
index 00000000..5f35c1c2
--- /dev/null
+++ b/meta-isar/recipes-bsp/opensbi/files/starfive-visionfive2-rules.tmpl
@@ -0,0 +1,17 @@ 
+#!/usr/bin/make -f
+
+ifneq ($(DEB_BUILD_GNU_TYPE),$(DEB_HOST_GNU_TYPE))
+export CROSS_COMPILE=$(DEB_HOST_GNU_TYPE)-
+endif
+
+UBOOT_DTB_FILE := /usr/share/u-boot/starfive-visionfive2/${DTB_UBOOT_JH7110_VF2}
+FW_TEXT_START := 0x40000000
+
+override_dh_auto_build:
+	CFLAGS= LDFLAGS= $(MAKE) $(PARALLEL_MAKE) PLATFORM=generic \
+		FW_PAYLOAD_PATH=/usr/lib/u-boot/starfive-visionfive2/u-boot.bin \
+		FW_FDT_PATH=$(UBOOT_DTB_FILE) \
+		FW_TEXT_START=$(FW_TEXT_START)
+
+%:
+	dh $@
diff --git a/meta-isar/recipes-bsp/opensbi/opensbi-starfive-visionfive2_1.2+20230107.bb b/meta-isar/recipes-bsp/opensbi/opensbi-starfive-visionfive2_1.2+20230107.bb
new file mode 100644
index 00000000..e7d767c9
--- /dev/null
+++ b/meta-isar/recipes-bsp/opensbi/opensbi-starfive-visionfive2_1.2+20230107.bb
@@ -0,0 +1,31 @@ 
+#
+# Copyright (c) Siemens AG, 2023
+#
+# SPDX-License-Identifier: MIT
+
+inherit dpkg
+
+DESCRIPTION = "OpenSBI firmware for StarFive VisionFive 2"
+
+SRC_URI = " \
+    git://github.com/riscv-software-src/opensbi.git;destsuffix=opensbi-${PV};protocol=https;branch=master \
+    file://starfive-visionfive2-rules.tmpl"
+# required patches are not yet part of a release, but will be in 1.3
+SRCREV = "c8ea836ee33eb778f48f780412e147386dac5301"
+
+S = "${WORKDIR}/opensbi-${PV}"
+TEMPLATE_FILES += "starfive-visionfive2-rules.tmpl"
+TEMPLATE_VARS += "DTB_UBOOT_JH7110_VF2"
+
+DEPENDS = "u-boot-starfive-visionfive2"
+DEBIAN_BUILD_DEPENDS = " \
+    u-boot-starfive-visionfive2, \
+    u-boot-starfive-visionfive2-dev"
+
+do_prepare_build[cleandirs] += "${S}/debian"
+do_prepare_build() {
+    cp ${WORKDIR}/starfive-visionfive2-rules ${WORKDIR}/rules
+    deb_debianize
+
+    echo "build/platform/generic/firmware/fw_payload.bin /usr/lib/opensbi/starfive-visionfive2/" > ${S}/debian/install
+}