diff --git a/kas/machine/Kconfig b/kas/machine/Kconfig
index 8c334a8f..d96c9f0a 100644
--- a/kas/machine/Kconfig
+++ b/kas/machine/Kconfig
@@ -216,6 +216,7 @@ config MACHINE_STM32MP15X
 	bool "stm32mp15x"
 	select DISTRO_DEBIAN
 	select CODENAME_BULLSEYE
+	select CODENAME_BOOKWORM
 	select ARCH_ARMHF
 
 config MACHINE_VIRTUALBOX
diff --git a/meta-isar/conf/machine/stm32mp15x.conf b/meta-isar/conf/machine/stm32mp15x.conf
index b10dead3..7a79fcd7 100644
--- a/meta-isar/conf/machine/stm32mp15x.conf
+++ b/meta-isar/conf/machine/stm32mp15x.conf
@@ -1,5 +1,6 @@
 #
-# Copyright (c) Siemens AG, 2020
+# Copyright (c) Siemens AG, 2020-2023
+# Copyright (c) 2021-2025 ilbers GmbH
 #
 # SPDX-License-Identifier: MIT
 
@@ -7,13 +8,13 @@ DISTRO_ARCH ?= "armhf"
 
 KERNEL_NAME ?= "mainline"
 
-U_BOOT_CONFIG:stm32mp15x = "stm32mp15_trusted_defconfig"
-U_BOOT_BIN:stm32mp15x = "u-boot.stm32"
+U_BOOT_CONFIG:stm32mp15x = "stm32mp15_defconfig"
+U_BOOT_BIN:stm32mp15x = "u-boot-nodtb.bin u-boot.dtb"
 
 IMAGE_FSTYPES ?= "wic"
 WKS_FILE ?= "stm32mp15x.wks.in"
-IMAGER_INSTALL:wic += "trusted-firmware-a-stm32mp15x optee-os-stm32mp15x u-boot-stm32mp15x"
-IMAGER_BUILD_DEPS += "trusted-firmware-a-stm32mp15x optee-os-stm32mp15x u-boot-stm32mp15x"
+IMAGER_INSTALL:wic += "trusted-firmware-a-stm32mp15x"
+IMAGER_BUILD_DEPS += "trusted-firmware-a-stm32mp15x"
 
 IMAGE_INSTALL += "u-boot-script \
     optee-examples-stm32mp15x-acipher-host \
diff --git a/meta-isar/conf/mc.conf b/meta-isar/conf/mc.conf
index 55969c7b..45de8557 100644
--- a/meta-isar/conf/mc.conf
+++ b/meta-isar/conf/mc.conf
@@ -50,6 +50,7 @@ BBMULTICONFIG = " \
     nanopi-neo-bookworm \
     nanopi-neo-efi-bookworm \
     stm32mp15x-bullseye \
+    stm32mp15x-bookworm \
     virtualbox-bullseye \
     virtualbox-bookworm \
     x86-pc-bookworm \
diff --git a/meta-isar/conf/multiconfig/stm32mp15x-bookworm.conf b/meta-isar/conf/multiconfig/stm32mp15x-bookworm.conf
new file mode 100644
index 00000000..d699d0fe
--- /dev/null
+++ b/meta-isar/conf/multiconfig/stm32mp15x-bookworm.conf
@@ -0,0 +1,5 @@
+# This software is a part of ISAR.

+# Copyright (C) 2025 ilbers GmbH

+

+MACHINE ?= "stm32mp15x"

+DISTRO ?= "debian-bookworm"

diff --git a/meta-isar/recipes-bsp/optee-os/optee-os-stm32mp15x_3.21.0.inc b/meta-isar/recipes-bsp/optee-os/optee-os-stm32mp15x_3.21.0.inc
index 2f55f36f..c5481ba9 100644
--- a/meta-isar/recipes-bsp/optee-os/optee-os-stm32mp15x_3.21.0.inc
+++ b/meta-isar/recipes-bsp/optee-os/optee-os-stm32mp15x_3.21.0.inc
@@ -1,5 +1,6 @@
 #
 # Copyright (c) Siemens AG, 2020-2023
+# Copyright (c) 2023-2025 ilbers GmbH
 #
 # SPDX-License-Identifier: MIT
 
@@ -10,11 +11,11 @@ S = "${WORKDIR}/optee_os-${PV}"
 
 DEBIAN_BUILD_DEPENDS += ", device-tree-compiler, python3-cryptography:native"
 
-OPTEE_PLATFORM = "stm32mp1"
+OPTEE_PLATFORM = "stm32mp1-157A_DK1"
 OPTEE_EXTRA_BUILDARGS = " \
     TEE_IMPL_VERSION=${PV} \
-    ARCH=arm CFG_EMBED_DTB_SOURCE_FILE=stm32mp157c-ev1.dts \
+    ARCH=arm CFG_EMBED_DTB_SOURCE_FILE=stm32mp157a-dk1.dts \
     CFG_TEE_CORE_LOG_LEVEL=2"
-OPTEE_BINARIES = "tee-header_v2.stm32 tee-pageable_v2.stm32 tee-pager_v2.stm32"
+OPTEE_BINARIES = "tee-header_v2.bin tee-pageable_v2.bin tee-pager_v2.bin"
 
 COMPATIBLE_MACHINE = "stm32mp15x"
diff --git a/meta-isar/recipes-bsp/trusted-firmware-a/files/0001-feat-build-add-support-for-new-binutils-versions.patch b/meta-isar/recipes-bsp/trusted-firmware-a/files/0001-feat-build-add-support-for-new-binutils-versions.patch
new file mode 100644
index 00000000..54ea992e
--- /dev/null
+++ b/meta-isar/recipes-bsp/trusted-firmware-a/files/0001-feat-build-add-support-for-new-binutils-versions.patch
@@ -0,0 +1,65 @@
+From a2228a87cc528bc5238fd7d7b5edd1899abe72d8 Mon Sep 17 00:00:00 2001

+From: Marco Felsch <m.felsch@pengutronix.de>

+Date: Wed, 9 Nov 2022 12:59:09 +0100

+Subject: [PATCH] feat(build): add support for new binutils versions

+

+Users of GNU ld (BPF) from binutils 2.39+ will observe multiple instaces

+of a new warning when linking the bl*.elf in the form:

+

+  ld.bfd: warning: stm32mp1_helper.o: missing .note.GNU-stack section implies executable stack

+  ld.bfd: NOTE: This behaviour is deprecated and will be removed in a future version of the linker

+  ld.bfd: warning: bl2.elf has a LOAD segment with RWX permissions

+  ld.bfd: warning: bl32.elf has a LOAD segment with RWX permissions

+

+These new warnings are enbaled by default to secure elf binaries:

+ - https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=ba951afb99912da01a6e8434126b8fac7aa75107

+ - https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=0d38576a34ec64a1b4500c9277a8e9d0f07e6774

+

+Fix it in a similar way to what the Linux kernel does, see:

+https://lore.kernel.org/all/20220810222442.2296651-1-ndesaulniers@google.com/

+

+Following the reasoning there, we set "-z noexecstack" for all linkers

+(although LLVM's LLD defaults to it) and optional add

+--no-warn-rwx-segments since this a ld.bfd related.

+

+Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

+Signed-off-by: Robert Schwebel <r.schwebel@pengutronix.de>

+Change-Id: I9430f5fa5036ca88da46cd3b945754d62616b617

+Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/293133

+ACI: CITOOLS <MDG-smet-aci-reviews@list.st.com>

+ACI: CIBUILD <MDG-smet-aci-builds@list.st.com>

+Tested-by: Yann GAUTIER <yann.gautier@foss.st.com>

+Reviewed-by: Yann GAUTIER <yann.gautier@foss.st.com>

+Domain-Review: Yann GAUTIER <yann.gautier@foss.st.com>

+---

+ Makefile | 7 ++++++-

+ 1 file changed, 6 insertions(+), 1 deletion(-)

+

+diff --git a/Makefile b/Makefile

+index 43ff4672f..841207559 100644

+--- a/Makefile

++++ b/Makefile

+@@ -417,6 +417,8 @@ endif

+ 

+ GCC_V_OUTPUT		:=	$(shell $(CC) -v 2>&1)

+ 

++TF_LDFLAGS		+=	-z noexecstack

++

+ # LD = armlink

+ ifneq ($(findstring armlink,$(notdir $(LD))),)

+ TF_LDFLAGS		+=	--diag_error=warning --lto_level=O1

+@@ -443,7 +445,10 @@ TF_LDFLAGS		+=	$(subst --,-Xlinker --,$(TF_LDFLAGS_$(ARCH)))

+ 

+ # LD = gcc-ld (ld) or llvm-ld (ld.lld) or other

+ else

+-TF_LDFLAGS		+=	--fatal-warnings -O1

++# With ld.bfd version 2.39 and newer new warnings are added. Skip those since we

++# are not loaded by a elf loader.

++TF_LDFLAGS		+=	$(call ld_option, --no-warn-rwx-segments)

++TF_LDFLAGS		+=	-O1

+ TF_LDFLAGS		+=	--gc-sections

+ # ld.lld doesn't recognize the errata flags,

+ # therefore don't add those in that case

+-- 

+2.39.2

+

diff --git a/meta-isar/recipes-bsp/trusted-firmware-a/files/0001-feat-stm32mp15-fdts-add-stm32mp157d-dk1-board.patch b/meta-isar/recipes-bsp/trusted-firmware-a/files/0001-feat-stm32mp15-fdts-add-stm32mp157d-dk1-board.patch
new file mode 100644
index 00000000..4cfe411e
--- /dev/null
+++ b/meta-isar/recipes-bsp/trusted-firmware-a/files/0001-feat-stm32mp15-fdts-add-stm32mp157d-dk1-board.patch
@@ -0,0 +1,55 @@
+From df393282a458dec817a0f5c9d6c6f399d2cc0382 Mon Sep 17 00:00:00 2001
+From: Yann Gautier <yann.gautier@st.com>
+Date: Fri, 21 Oct 2022 11:38:10 +0200
+Subject: [PATCH] feat(stm32mp15-fdts): add stm32mp157d-dk1 board
+
+This commit adds stm32mp157d-dk1 board support. This board embeds a
+STM32MP157D SOC. This SOC contains the same level of feature than a
+STM32MP157A SOC but A7 clock frequency can reach 800MHz.
+
+Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
+Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
+Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
+Change-Id: I05137af3ec475c49ee6f99b9a23f23130ea5892a
+---
+ fdts/stm32mp157d-dk1.dts | 28 ++++++++++++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+ create mode 100644 fdts/stm32mp157d-dk1.dts
+
+diff --git a/fdts/stm32mp157d-dk1.dts b/fdts/stm32mp157d-dk1.dts
+new file mode 100644
+index 000000000..2b7dde544
+--- /dev/null
++++ b/fdts/stm32mp157d-dk1.dts
+@@ -0,0 +1,28 @@
++// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
++/*
++ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
++ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
++ */
++
++/dts-v1/;
++
++#include "stm32mp157.dtsi"
++#include "stm32mp15xd.dtsi"
++#include "stm32mp15-pinctrl.dtsi"
++#include "stm32mp15xxac-pinctrl.dtsi"
++#include "stm32mp15xx-dkx.dtsi"
++
++/ {
++	model = "STMicroelectronics STM32MP157D-DK1 Discovery Board";
++	compatible = "st,stm32mp157d-dk1", "st,stm32mp157";
++
++	aliases {
++		serial0 = &uart4;
++		serial1 = &usart3;
++		serial2 = &uart7;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++};
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/trusted-firmware-a/files/0001-feat-stm32mp15-fdts-fulfill-diversity-for-STM32M15x-.patch b/meta-isar/recipes-bsp/trusted-firmware-a/files/0001-feat-stm32mp15-fdts-fulfill-diversity-for-STM32M15x-.patch
new file mode 100644
index 00000000..a3e4cec6
--- /dev/null
+++ b/meta-isar/recipes-bsp/trusted-firmware-a/files/0001-feat-stm32mp15-fdts-fulfill-diversity-for-STM32M15x-.patch
@@ -0,0 +1,90 @@
+From 523dbda922eaace7724b765035e3358735151eb5 Mon Sep 17 00:00:00 2001
+From: Yann Gautier <yann.gautier@st.com>
+Date: Fri, 21 Oct 2022 11:22:37 +0200
+Subject: [PATCH] feat(stm32mp15-fdts): fulfill diversity for STM32M15x SOCs
+
+This commit creates new files to manage security features and supported OPP
+on STM32MP15x SOCs. On STM32MP15xY, "Y" gives information:
+ -Y = A means no cryp IP and no secure boot + A7-CPU@650MHz.
+ -Y = C means cryp IP + optee + secure boot + A7-CPU@650MHz.
+ -Y = D means no cryp IP and no secure boot + A7-CPU@800MHz.
+ -Y = F means cryp IP + optee + secure boot + A7-CPU@800MHz.
+
+Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
+Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
+Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
+Change-Id: Ic9fa8f714ba8d8095664c55dbcadfae49e9e2f4f
+---
+ fdts/stm32mp15xa.dtsi |  5 +++++
+ fdts/stm32mp15xc.dtsi |  2 ++
+ fdts/stm32mp15xd.dtsi |  5 +++++
+ fdts/stm32mp15xf.dtsi | 20 ++++++++++++++++++++
+ 4 files changed, 32 insertions(+)
+ create mode 100644 fdts/stm32mp15xa.dtsi
+ create mode 100644 fdts/stm32mp15xd.dtsi
+ create mode 100644 fdts/stm32mp15xf.dtsi
+
+diff --git a/fdts/stm32mp15xa.dtsi b/fdts/stm32mp15xa.dtsi
+new file mode 100644
+index 000000000..cc6456e71
+--- /dev/null
++++ b/fdts/stm32mp15xa.dtsi
+@@ -0,0 +1,5 @@
++// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
++/*
++ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
++ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
++ */
+diff --git a/fdts/stm32mp15xc.dtsi b/fdts/stm32mp15xc.dtsi
+index b06a55a2f..f729b0d1b 100644
+--- a/fdts/stm32mp15xc.dtsi
++++ b/fdts/stm32mp15xc.dtsi
+@@ -4,6 +4,8 @@
+  * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+  */
+ 
++#include "stm32mp15xa.dtsi"
++
+ / {
+ 	soc {
+ 		cryp1: cryp@54001000 {
+diff --git a/fdts/stm32mp15xd.dtsi b/fdts/stm32mp15xd.dtsi
+new file mode 100644
+index 000000000..cc6456e71
+--- /dev/null
++++ b/fdts/stm32mp15xd.dtsi
+@@ -0,0 +1,5 @@
++// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
++/*
++ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
++ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
++ */
+diff --git a/fdts/stm32mp15xf.dtsi b/fdts/stm32mp15xf.dtsi
+new file mode 100644
+index 000000000..ae4a14af6
+--- /dev/null
++++ b/fdts/stm32mp15xf.dtsi
+@@ -0,0 +1,20 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
++ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
++ */
++
++#include "stm32mp15xd.dtsi"
++
++/ {
++	soc {
++		cryp1: cryp@54001000 {
++			compatible = "st,stm32mp1-cryp";
++			reg = <0x54001000 0x400>;
++			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&rcc CRYP1>;
++			resets = <&rcc CRYP1_R>;
++			status = "disabled";
++		};
++	};
++};
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/trusted-firmware-a/trusted-firmware-a-stm32mp15x_2.4.bb b/meta-isar/recipes-bsp/trusted-firmware-a/trusted-firmware-a-stm32mp15x_2.4.bb
deleted file mode 100644
index b36dc3ee..00000000
--- a/meta-isar/recipes-bsp/trusted-firmware-a/trusted-firmware-a-stm32mp15x_2.4.bb
+++ /dev/null
@@ -1,23 +0,0 @@
-#
-# Copyright (c) Siemens AG, 2020
-#
-# SPDX-License-Identifier: MIT
-
-require recipes-bsp/trusted-firmware-a/trusted-firmware-a-custom.inc
-
-SRC_URI += "https://github.com/ARM-software/arm-trusted-firmware/archive/v${PV}.tar.gz;downloadfilename=arm-trusted-firmware-${PV}.tar.gz"
-SRC_URI[sha256sum] = "4bfda9fdbe5022f2e88ad3344165f7d38a8ae4a0e2d91d44d9a1603425cc642d"
-
-S = "${WORKDIR}/arm-trusted-firmware-${PV}"
-
-DEBIAN_BUILD_DEPENDS += ", device-tree-compiler"
-
-TF_A_PLATFORM = "stm32mp1"
-TF_A_EXTRA_BUILDARGS = " \
-    ARCH=aarch32 ARM_ARCH_MAJOR=7 AARCH32_SP=optee \
-    STM32MP_SDMMC=1 STM32MP_EMMC=1 \
-    STM32MP_RAW_NAND=1 STM32MP_SPI_NAND=1 STM32MP_SPI_NOR=1 \
-    DTB_FILE_NAME=stm32mp157c-ev1.dtb"
-TF_A_BINARIES = "release/tf-a-stm32mp157c-ev1.stm32"
-
-COMPATIBLE_MACHINE = "stm32mp15x"
diff --git a/meta-isar/recipes-bsp/trusted-firmware-a/trusted-firmware-a-stm32mp15x_2.8.bb b/meta-isar/recipes-bsp/trusted-firmware-a/trusted-firmware-a-stm32mp15x_2.8.bb
new file mode 100644
index 00000000..88d07eba
--- /dev/null
+++ b/meta-isar/recipes-bsp/trusted-firmware-a/trusted-firmware-a-stm32mp15x_2.8.bb
@@ -0,0 +1,41 @@
+#
+# Copyright (c) Siemens AG, 2020
+# Copyright (c) 2023-2025 ilbers GmbH
+#
+# SPDX-License-Identifier: MIT
+
+require recipes-bsp/trusted-firmware-a/trusted-firmware-a-custom.inc
+
+SRC_URI += "https://github.com/ARM-software/arm-trusted-firmware/archive/v${PV}.tar.gz;downloadfilename=arm-trusted-firmware-${PV}.tar.gz \
+    file://0001-feat-stm32mp15-fdts-add-stm32mp157d-dk1-board.patch \
+    file://0001-feat-stm32mp15-fdts-fulfill-diversity-for-STM32M15x-.patch \
+    file://0001-feat-build-add-support-for-new-binutils-versions.patch"
+
+SRC_URI[sha256sum] = "42256fa354f32b09972e72e0570a0f73698785927f93163b1d1308c485fcb4a6"
+
+S = "${WORKDIR}/arm-trusted-firmware-${PV}"
+
+DEPENDS = "u-boot-${MACHINE} optee-os-${MACHINE}"
+
+DEBIAN_BUILD_DEPENDS += ", optee-os-${MACHINE}, u-boot-${MACHINE}, \
+    device-tree-compiler, git, libssl-dev:native"
+
+TF_A_PLATFORM = "stm32mp1"
+
+FIP_EXTRA_BUILDARGS = "AARCH32_SP=optee \
+    BL32=/usr/lib/optee-os/${MACHINE}/tee-header_v2.bin \
+    BL32_EXTRA1=/usr/lib/optee-os/${MACHINE}/tee-pager_v2.bin \
+    BL32_EXTRA2=/usr/lib/optee-os/${MACHINE}/tee-pageable_v2.bin \
+    BL33=/usr/lib/u-boot/${MACHINE}/u-boot-nodtb.bin \
+    BL33_CFG=/usr/lib/u-boot/${MACHINE}/u-boot.dtb \
+    FW_CONFIG=fdts/stm32mp157d-dk1-fw-config.dts \
+    all fip"
+
+TF_A_EXTRA_BUILDARGS = " \
+    ARCH=aarch32 ARM_ARCH_MAJOR=7 \
+    STM32MP_SDMMC=1 DTB_FILE_NAME=stm32mp157d-dk1.dtb \
+    ${FIP_EXTRA_BUILDARGS}"
+
+TF_A_BINARIES = "release/tf-a-stm32mp157d-dk1.stm32 release/fip.bin"
+
+COMPATIBLE_MACHINE = "stm32mp15x"
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0003-drivers-tee-optee-remove-unused-probe-local-variable.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0003-drivers-tee-optee-remove-unused-probe-local-variable.patch
new file mode 100644
index 00000000..5a68a726
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0003-drivers-tee-optee-remove-unused-probe-local-variable.patch
@@ -0,0 +1,42 @@
+From b16145419fbde7ce36a51dfddde11ab4b0bd22a5 Mon Sep 17 00:00:00 2001
+From: Etienne Carriere <etienne.carriere@linaro.org>
+Date: Tue, 26 Jul 2022 16:21:41 +0200
+Subject: [PATCH 003/117] drivers: tee: optee: remove unused probe local
+ variable
+
+Removes local variable child in optee_probe() that is not used.
+
+[Backport of commit fd0d7a6c88fe ("drivers: tee: optee: remove unused probe local variable")]
+
+Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
+Change-Id: I0c086249928f0857c63ffb56b7868668f23dbd65
+---
+ drivers/tee/optee/core.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c
+index a89d62aaf0..c1f5fc4c7a 100644
+--- a/drivers/tee/optee/core.c
++++ b/drivers/tee/optee/core.c
+@@ -642,7 +642,6 @@ static int optee_probe(struct udevice *dev)
+ {
+ 	struct optee_pdata *pdata = dev_get_plat(dev);
+ 	u32 sec_caps;
+-	struct udevice *child;
+ 	int ret;
+ 
+ 	if (!is_optee_api(pdata->invoke_fn)) {
+@@ -673,7 +672,7 @@ static int optee_probe(struct udevice *dev)
+ 	 * only bind the drivers associated to the supported OP-TEE TA
+ 	 */
+ 	if (IS_ENABLED(CONFIG_RNG_OPTEE)) {
+-		ret = device_bind_driver(dev, "optee-rng", "optee-rng", &child);
++		ret = device_bind_driver(dev, "optee-rng", "optee-rng", NULL);
+ 		if (ret)
+ 			return ret;
+ 	}
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0004-drivers-tee-optee-discover-OP-TEE-services.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0004-drivers-tee-optee-discover-OP-TEE-services.patch
new file mode 100644
index 00000000..f4322d0e
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0004-drivers-tee-optee-discover-OP-TEE-services.patch
@@ -0,0 +1,307 @@
+From 4049f440314bd2de5fdb43ec86096f94e8bbdda0 Mon Sep 17 00:00:00 2001
+From: Etienne Carriere <etienne.carriere@linaro.org>
+Date: Tue, 26 Jul 2022 16:21:42 +0200
+Subject: [PATCH 004/117] drivers: tee: optee: discover OP-TEE services
+
+This change defines resources for OP-TEE service drivers to register
+themselves for being bound to when OP-TEE firmware reports the related
+service is supported. OP-TEE services are discovered during optee
+driver probe sequence which mandates optee driver is always probe once
+bound.
+
+Discovery of optee services and binding to related U-Boot drivers is
+embedded upon configuration switch CONFIG_OPTEE_SERVICE_DISCOVERY.
+
+[Backport of commit 94ccfb78a4d6 ("drivers: tee: optee: discover OP-TEE services")]
+
+Cc: Jens Wiklander <jens.wiklander@linaro.org>
+Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
+Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Change-Id: Iffad3ca50359fdfb98f47c972cc1816e179c5506
+---
+ drivers/tee/optee/Kconfig   |   8 ++
+ drivers/tee/optee/core.c    | 171 ++++++++++++++++++++++++++++++++++--
+ include/tee/optee_service.h |  34 +++++++
+ 3 files changed, 208 insertions(+), 5 deletions(-)
+ create mode 100644 include/tee/optee_service.h
+
+diff --git a/drivers/tee/optee/Kconfig b/drivers/tee/optee/Kconfig
+index d03028070b..9dc65b0501 100644
+--- a/drivers/tee/optee/Kconfig
++++ b/drivers/tee/optee/Kconfig
+@@ -37,6 +37,14 @@ config OPTEE_TA_SCP03
+ 	help
+ 	  Enables support for controlling (enabling, provisioning) the
+ 	  Secure Channel Protocol 03 operation in the OP-TEE SCP03 TA.
++
++config OPTEE_SERVICE_DISCOVERY
++	bool "OP-TEE service discovery"
++	default y
++	help
++	  This implements automated driver binding of OP-TEE service drivers by
++	  requesting OP-TEE firmware to enumerate its hosted services.
++
+ endmenu
+ 
+ endif
+diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c
+index c1f5fc4c7a..9240277579 100644
+--- a/drivers/tee/optee/core.c
++++ b/drivers/tee/optee/core.c
+@@ -14,6 +14,7 @@
+ #include <linux/arm-smccc.h>
+ #include <linux/err.h>
+ #include <linux/io.h>
++#include <tee/optee_service.h>
+ 
+ #include "optee_smc.h"
+ #include "optee_msg.h"
+@@ -22,6 +23,25 @@
+ #define PAGELIST_ENTRIES_PER_PAGE \
+ 	((OPTEE_MSG_NONCONTIG_PAGE_SIZE / sizeof(u64)) - 1)
+ 
++/*
++ * PTA_DEVICE_ENUM interface exposed by OP-TEE to discover enumerated services
++ */
++#define PTA_DEVICE_ENUM		{ 0x7011a688, 0xddde, 0x4053, \
++				  { 0xa5, 0xa9, 0x7b, 0x3c, 0x4d, 0xdf, 0x13, 0xb8 } }
++/*
++ * PTA_CMD_GET_DEVICES - List services without supplicant dependencies
++ *
++ * [out]    memref[0]: List of the UUIDs of service enumerated by OP-TEE
++ */
++#define PTA_CMD_GET_DEVICES		0x0
++
++/*
++ * PTA_CMD_GET_DEVICES_SUPP - List services depending on tee supplicant
++ *
++ * [out]    memref[0]: List of the UUIDs of service enumerated by OP-TEE
++ */
++#define PTA_CMD_GET_DEVICES_SUPP	0x1
++
+ typedef void (optee_invoke_fn)(unsigned long, unsigned long, unsigned long,
+ 			       unsigned long, unsigned long, unsigned long,
+ 			       unsigned long, unsigned long,
+@@ -42,6 +62,134 @@ struct rpc_param {
+ 	u32	a7;
+ };
+ 
++static struct optee_service *find_service_driver(const struct tee_optee_ta_uuid *uuid)
++{
++	struct optee_service *service;
++	u8 loc_uuid[TEE_UUID_LEN];
++	size_t service_cnt, idx;
++
++	service_cnt = ll_entry_count(struct optee_service, optee_service);
++	service = ll_entry_start(struct optee_service, optee_service);
++
++	for (idx = 0; idx < service_cnt; idx++, service++) {
++		tee_optee_ta_uuid_to_octets(loc_uuid, &service->uuid);
++		if (!memcmp(uuid, loc_uuid, sizeof(uuid)))
++			return service;
++	}
++
++	return NULL;
++}
++
++static int bind_service_list(struct udevice *dev, struct tee_shm *service_list, size_t count)
++{
++	const struct tee_optee_ta_uuid *service_uuid = (const void *)service_list->addr;
++	struct optee_service *service;
++	size_t idx;
++	int ret;
++
++	for (idx = 0; idx < count; idx++) {
++		service = find_service_driver(service_uuid + idx);
++		if (!service)
++			continue;
++
++		ret = device_bind_driver(dev, service->driver_name, service->driver_name, NULL);
++		if (ret) {
++			dev_warn(dev, "%s was not bound: %d, ignored\n", service->driver_name, ret);
++			continue;
++		}
++	}
++
++	return 0;
++}
++
++static int __enum_services(struct udevice *dev, struct tee_shm *shm, size_t *shm_size, u32 tee_sess)
++{
++	struct tee_invoke_arg arg = { };
++	struct tee_param param = { };
++	int ret = 0;
++
++	arg.func = PTA_CMD_GET_DEVICES;
++	arg.session = tee_sess;
++
++	/* Fill invoke cmd params */
++	param.attr = TEE_PARAM_ATTR_TYPE_MEMREF_OUTPUT;
++	param.u.memref.shm = shm;
++	param.u.memref.size = *shm_size;
++
++	ret = tee_invoke_func(dev, &arg, 1, &param);
++	if (ret || (arg.ret && arg.ret != TEE_ERROR_SHORT_BUFFER)) {
++		dev_err(dev, "PTA_CMD_GET_DEVICES invoke function err: 0x%x\n", arg.ret);
++		return -EINVAL;
++	}
++
++	*shm_size = param.u.memref.size;
++
++	return 0;
++}
++
++static int enum_services(struct udevice *dev, struct tee_shm **shm, size_t *count, u32 tee_sess)
++{
++	size_t shm_size = 0;
++	int ret;
++
++	ret = __enum_services(dev, NULL, &shm_size, tee_sess);
++	if (ret)
++		return ret;
++
++	ret = tee_shm_alloc(dev, shm_size, 0, shm);
++	if (ret) {
++		dev_err(dev, "Failed to allocated shared memory: %d\n", ret);
++		return ret;
++	}
++
++	ret = __enum_services(dev, *shm, &shm_size, tee_sess);
++	if (!ret)
++		*count = shm_size / sizeof(struct tee_optee_ta_uuid);
++
++	return ret;
++}
++
++static int open_enum_session(struct udevice *dev, u32 *tee_sess)
++{
++	const struct tee_optee_ta_uuid pta_uuid = PTA_DEVICE_ENUM;
++	struct tee_open_session_arg arg = { };
++	int ret;
++
++	tee_optee_ta_uuid_to_octets(arg.uuid, &pta_uuid);
++
++	ret = tee_open_session(dev, &arg, 0, NULL);
++	if (ret || arg.ret) {
++		if (!ret)
++			ret = -EIO;
++		return ret;
++	}
++
++	*tee_sess = arg.session;
++
++	return 0;
++}
++
++static int bind_service_drivers(struct udevice *dev)
++{
++	struct tee_shm *service_list = NULL;
++	size_t service_count;
++	u32 tee_sess;
++	int ret;
++
++	ret = open_enum_session(dev, &tee_sess);
++	if (ret)
++		return ret;
++
++	ret = enum_services(dev, &service_list, &service_count, tee_sess);
++	if (!ret)
++		ret = bind_service_list(dev, service_list, service_count);
++
++	tee_shm_free(service_list);
++	tee_close_session(dev, tee_sess);
++
++	return ret;
++}
++
+ /**
+  * reg_pair_to_ptr() - Make a pointer of 2 32-bit values
+  * @reg0:	High bits of the pointer
+@@ -638,6 +786,14 @@ static int optee_of_to_plat(struct udevice *dev)
+ 	return 0;
+ }
+ 
++static int optee_bind(struct udevice *dev)
++{
++	if (IS_ENABLED(CONFIG_OPTEE_SERVICE_DISCOVERY))
++		dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
++
++	return 0;
++}
++
+ static int optee_probe(struct udevice *dev)
+ {
+ 	struct optee_pdata *pdata = dev_get_plat(dev);
+@@ -667,11 +823,15 @@ static int optee_probe(struct udevice *dev)
+ 		return -ENOENT;
+ 	}
+ 
+-	/*
+-	 * in U-Boot, the discovery of TA on the TEE bus is not supported:
+-	 * only bind the drivers associated to the supported OP-TEE TA
+-	 */
+-	if (IS_ENABLED(CONFIG_RNG_OPTEE)) {
++	if (IS_ENABLED(CONFIG_OPTEE_SERVICE_DISCOVERY)) {
++		ret = bind_service_drivers(dev);
++		if (ret)
++			return ret;
++	} else if (IS_ENABLED(CONFIG_RNG_OPTEE)) {
++		/*
++		 * Discovery of TAs on the TEE bus is not supported in U-Boot:
++		 * only bind the drivers associated to the supported OP-TEE TA
++		 */
+ 		ret = device_bind_driver(dev, "optee-rng", "optee-rng", NULL);
+ 		if (ret)
+ 			return ret;
+@@ -691,6 +851,7 @@ U_BOOT_DRIVER(optee) = {
+ 	.of_match = optee_match,
+ 	.of_to_plat = optee_of_to_plat,
+ 	.probe = optee_probe,
++	.bind = optee_bind,
+ 	.ops = &optee_ops,
+ 	.plat_auto	= sizeof(struct optee_pdata),
+ 	.priv_auto	= sizeof(struct optee_private),
+diff --git a/include/tee/optee_service.h b/include/tee/optee_service.h
+new file mode 100644
+index 0000000000..fca468af7c
+--- /dev/null
++++ b/include/tee/optee_service.h
+@@ -0,0 +1,34 @@
++/* SPDX-License-Identifier: BSD-2-Clause */
++/*
++ * (C) Copyright 2022 Linaro Limited
++ */
++
++#ifndef _OPTEE_SERVICE_H
++#define _OPTEE_SERVICE_H
++
++/*
++ * struct optee_service - Discoverable OP-TEE service
++ *
++ * @driver_name - Name of the related driver
++ * @uuid - UUID of the OP-TEE service related to the driver
++ *
++ * Use macro OPTEE_SERVICE_DRIVER() to register a driver related to an
++ * OP-TEE service discovered when driver asks OP-TEE services enumaration.
++ */
++struct optee_service {
++	const char *driver_name;
++	const struct tee_optee_ta_uuid uuid;
++};
++
++#ifdef CONFIG_OPTEE_SERVICE_DISCOVERY
++#define OPTEE_SERVICE_DRIVER(__name, __uuid, __drv_name) \
++	ll_entry_declare(struct optee_service, __name, optee_service) = { \
++		.uuid = __uuid, \
++		.driver_name = __drv_name, \
++	}
++#else
++#define OPTEE_SERVICE_DRIVER(__name, __uuid, __drv_name) \
++	static int __name##__COUNTER__ __always_unused
++#endif
++
++#endif /* _OPTEE_SERVICE_H */
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0005-drivers-rng-optee_rng-register-to-CONFIG_OPTEE_SERVI.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0005-drivers-rng-optee_rng-register-to-CONFIG_OPTEE_SERVI.patch
new file mode 100644
index 00000000..cb9954d4
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0005-drivers-rng-optee_rng-register-to-CONFIG_OPTEE_SERVI.patch
@@ -0,0 +1,69 @@
+From 7293566ef985a74b7eb0e6c7d4f6b082b2c9fd79 Mon Sep 17 00:00:00 2001
+From: Etienne Carriere <etienne.carriere@linaro.org>
+Date: Tue, 26 Jul 2022 16:21:43 +0200
+Subject: [PATCH 005/117] drivers: rng: optee_rng: register to
+ CONFIG_OPTEE_SERVICE_DISCOVERY
+
+Changes optee_rng driver to register itself has a OP-TEE service so
+that a device is bound for the driver when OP-TEE enumerates the
+PTA RNG service.
+
+[Backport of commit 57fb86a97d75 ("drivers: rng: optee_rng: register to CONFIG_OPTEE_SERVICE_DISCOVERY")]
+
+Cc: Sughosh Ganu <sughosh.ganu@linaro.org>
+Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
+Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Change-Id: I78467fd5dc22e4943b42ee98b11c1bbd680d074e
+---
+ drivers/rng/Kconfig     | 1 +
+ drivers/rng/optee_rng.c | 7 ++++++-
+ 2 files changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
+index 16143681da..5dcf68176a 100644
+--- a/drivers/rng/Kconfig
++++ b/drivers/rng/Kconfig
+@@ -41,6 +41,7 @@ config RNG_NPCM
+ config RNG_OPTEE
+ 	bool "OP-TEE based Random Number Generator support"
+ 	depends on DM_RNG && OPTEE
++	default y if OPTEE_SERVICE_DISCOVERY
+ 	help
+ 	  This driver provides support for the OP-TEE based Random Number
+ 	  Generator on ARM SoCs where hardware entropy sources are not
+diff --git a/drivers/rng/optee_rng.c b/drivers/rng/optee_rng.c
+index aa8ce864d3..410dfc053f 100644
+--- a/drivers/rng/optee_rng.c
++++ b/drivers/rng/optee_rng.c
+@@ -11,6 +11,9 @@
+ #include <dm/device.h>
+ #include <dm/device_compat.h>
+ #include <linux/sizes.h>
++#include <tee/optee_service.h>
++
++#define DRIVER_NAME	"optee-rng"
+ 
+ #define TEE_ERROR_HEALTH_TEST_FAIL	0x00000001
+ 
+@@ -35,6 +38,8 @@
+ #define TA_HWRNG_UUID { 0xab7a617c, 0xb8e7, 0x4d8f, \
+ 			{ 0x83, 0x01, 0xd0, 0x9b, 0x61, 0x03, 0x6b, 0x64 } }
+ 
++OPTEE_SERVICE_DRIVER(optee_rng, TA_HWRNG_UUID, DRIVER_NAME);
++
+ /** open_session_ta_hwrng() - Open session with hwrng Trusted App
+  *
+  * @dev:		device
+@@ -177,7 +182,7 @@ static const struct dm_rng_ops optee_rng_ops = {
+ };
+ 
+ U_BOOT_DRIVER(optee_rng) = {
+-	.name = "optee-rng",
++	.name = DRIVER_NAME,
+ 	.id = UCLASS_RNG,
+ 	.ops = &optee_rng_ops,
+ 	.probe = optee_rng_probe,
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0014-ARM-dts-stm32mp-alignment-with-v6.0-rc3.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0014-ARM-dts-stm32mp-alignment-with-v6.0-rc3.patch
new file mode 100644
index 00000000..93e8fa47
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0014-ARM-dts-stm32mp-alignment-with-v6.0-rc3.patch
@@ -0,0 +1,265 @@
+From be743405e7debb793ab4d269f1e70835dfa9d75c Mon Sep 17 00:00:00 2001
+From: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Date: Wed, 7 Sep 2022 13:42:23 +0200
+Subject: [PATCH 014/117] ARM: dts: stm32mp: alignment with v6.0-rc3
+
+Device tree alignment with Linux kernel v6.0-rc3:
+- ARM: dts: stm32: add support for USB2514B onboard hub on stm32mp15xx-dkx
+- ARM: dts: stm32: Add alternate pinmux for RCC pin
+- ARM: dts: stm32: Add alternate pinmux for DCMI pins
+- ARM: dts: stm32: Add alternate pinmux for SPI2 pins
+- ARM: dts: stm32: Fix SPI2 pinmux pin comments on stm32mp15
+- ARM: dts: stm32: add optee reserved memory on stm32mp135f-dk
+- ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP13
+- ARM: dts: stm32: remove the IPCC "wakeup" IRQ on stm32mp151
+
+[Backport of commit 152498d580ad ("ARM: dts: stm32mp: alignment with v6.0-rc3")]
+Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
+Change-Id: I38f76ef5708717d9d2311937d86fbb07f41da344
+---
+ arch/arm/dts/stm32mp13-u-boot.dtsi  | 10 +++--
+ arch/arm/dts/stm32mp131.dtsi        | 28 ++++++-------
+ arch/arm/dts/stm32mp135f-dk.dts     |  4 +-
+ arch/arm/dts/stm32mp15-pinctrl.dtsi | 64 ++++++++++++++++++++++++++---
+ arch/arm/dts/stm32mp151.dtsi        |  7 ++--
+ arch/arm/dts/stm32mp15xx-dkx.dtsi   |  8 ++++
+ 6 files changed, 91 insertions(+), 30 deletions(-)
+
+diff --git a/arch/arm/dts/stm32mp13-u-boot.dtsi b/arch/arm/dts/stm32mp13-u-boot.dtsi
+index 01552adb7c..47a43649bb 100644
+--- a/arch/arm/dts/stm32mp13-u-boot.dtsi
++++ b/arch/arm/dts/stm32mp13-u-boot.dtsi
+@@ -17,6 +17,12 @@
+ 		pinctrl0 = &pinctrl;
+ 	};
+ 
++	firmware {
++		optee {
++			u-boot,dm-pre-reloc;
++		};
++	};
++
+ 	/* need PSCI for sysreset during board_f */
+ 	psci {
+ 		u-boot,dm-pre-proper;
+@@ -82,10 +88,6 @@
+ 	u-boot,dm-pre-reloc;
+ };
+ 
+-&optee {
+-	u-boot,dm-pre-reloc;
+-};
+-
+ &pinctrl {
+ 	u-boot,dm-pre-reloc;
+ };
+diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi
+index 84e16bb2f2..a1c6d0d00b 100644
+--- a/arch/arm/dts/stm32mp131.dtsi
++++ b/arch/arm/dts/stm32mp131.dtsi
+@@ -27,21 +27,8 @@
+ 		interrupt-parent = <&intc>;
+ 	};
+ 
+-	scmi_sram: sram@2ffff000 {
+-		compatible = "mmio-sram";
+-		reg = <0x2ffff000 0x1000>;
+-		#address-cells = <1>;
+-		#size-cells = <1>;
+-		ranges = <0 0x2ffff000 0x1000>;
+-
+-		scmi_shm: scmi_shm@0 {
+-			compatible = "arm,scmi-shmem";
+-			reg = <0 0x80>;
+-		};
+-	};
+-
+ 	firmware {
+-		optee: optee {
++		optee {
+ 			method = "smc";
+ 			compatible = "linaro,optee-tz";
+ 		};
+@@ -151,6 +138,19 @@
+ 		interrupt-parent = <&intc>;
+ 		ranges;
+ 
++		scmi_sram: sram@2ffff000 {
++			compatible = "mmio-sram";
++			reg = <0x2ffff000 0x1000>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0 0x2ffff000 0x1000>;
++
++			scmi_shm: scmi-sram@0 {
++				compatible = "arm,scmi-shmem";
++				reg = <0 0x80>;
++			};
++		};
++
+ 		uart4: serial@40010000 {
+ 			compatible = "st,stm32h7-uart";
+ 			reg = <0x40010000 0x400>;
+diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts
+index f436ffab99..e6b8ffd332 100644
+--- a/arch/arm/dts/stm32mp135f-dk.dts
++++ b/arch/arm/dts/stm32mp135f-dk.dts
+@@ -31,8 +31,8 @@
+ 		#size-cells = <1>;
+ 		ranges;
+ 
+-		optee@de000000 {
+-			reg = <0xde000000 0x2000000>;
++		optee@dd000000 {
++			reg = <0xdd000000 0x3000000>;
+ 			no-map;
+ 		};
+ 	};
+diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi
+index d3ed10335d..2cc9341d43 100644
+--- a/arch/arm/dts/stm32mp15-pinctrl.dtsi
++++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi
+@@ -151,6 +151,43 @@
+ 		};
+ 	};
+ 
++	dcmi_pins_c: dcmi-2 {
++		pins {
++			pinmux = <STM32_PINMUX('A', 4,  AF13)>,/* DCMI_HSYNC */
++				 <STM32_PINMUX('B', 7,  AF13)>,/* DCMI_VSYNC */
++				 <STM32_PINMUX('A', 6,  AF13)>,/* DCMI_PIXCLK */
++				 <STM32_PINMUX('A', 9,  AF13)>,/* DCMI_D0 */
++				 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
++				 <STM32_PINMUX('E', 0, AF13)>,/* DCMI_D2 */
++				 <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
++				 <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
++				 <STM32_PINMUX('I', 4,  AF13)>,/* DCMI_D5 */
++				 <STM32_PINMUX('I', 6,  AF13)>,/* DCMI_D6 */
++				 <STM32_PINMUX('E', 6,  AF13)>,/* DCMI_D7 */
++				 <STM32_PINMUX('I', 1,  AF13)>,/* DCMI_D8 */
++				 <STM32_PINMUX('H', 7,  AF13)>;/* DCMI_D9 */
++			bias-pull-up;
++		};
++	};
++
++	dcmi_sleep_pins_c: dcmi-sleep-2 {
++		pins {
++			pinmux = <STM32_PINMUX('A', 4,  ANALOG)>,/* DCMI_HSYNC */
++				 <STM32_PINMUX('B', 7,  ANALOG)>,/* DCMI_VSYNC */
++				 <STM32_PINMUX('A', 6,  ANALOG)>,/* DCMI_PIXCLK */
++				 <STM32_PINMUX('A', 9,  ANALOG)>,/* DCMI_D0 */
++				 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
++				 <STM32_PINMUX('E', 0, ANALOG)>,/* DCMI_D2 */
++				 <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
++				 <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
++				 <STM32_PINMUX('I', 4,  ANALOG)>,/* DCMI_D5 */
++				 <STM32_PINMUX('I', 6,  ANALOG)>,/* DCMI_D6 */
++				 <STM32_PINMUX('E', 6,  ANALOG)>,/* DCMI_D7 */
++				 <STM32_PINMUX('I', 1,  ANALOG)>,/* DCMI_D8 */
++				 <STM32_PINMUX('H', 7,  ANALOG)>;/* DCMI_D9 */
++		};
++	};
++
+ 	ethernet0_rgmii_pins_a: rgmii-0 {
+ 		pins1 {
+ 			pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
+@@ -923,6 +960,21 @@
+ 		};
+ 	};
+ 
++	mco1_pins_a: mco1-0 {
++		pins {
++			pinmux = <STM32_PINMUX('A', 13, AF2)>; /* MCO1 */
++			bias-disable;
++			drive-push-pull;
++			slew-rate = <1>;
++		};
++	};
++
++	mco1_sleep_pins_a: mco1-sleep-0 {
++		pins {
++			pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* MCO1 */
++		};
++	};
++
+ 	mco2_pins_a: mco2-0 {
+ 		pins {
+ 			pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
+@@ -1814,30 +1866,30 @@
+ 
+ 	spi2_pins_a: spi2-0 {
+ 		pins1 {
+-			pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI1_SCK */
+-				 <STM32_PINMUX('I', 3, AF5)>; /* SPI1_MOSI */
++			pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */
++				 <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
+ 			bias-disable;
+ 			drive-push-pull;
+ 			slew-rate = <1>;
+ 		};
+ 
+ 		pins2 {
+-			pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI1_MISO */
++			pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
+ 			bias-disable;
+ 		};
+ 	};
+ 
+ 	spi2_pins_b: spi2-1 {
+ 		pins1 {
+-			pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI1_SCK */
+-				 <STM32_PINMUX('I', 3, AF5)>; /* SPI1_MOSI */
++			pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */
++				 <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
+ 			bias-disable;
+ 			drive-push-pull;
+ 			slew-rate = <1>;
+ 		};
+ 
+ 		pins2 {
+-			pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI1_MISO */
++			pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
+ 			bias-disable;
+ 		};
+ 	};
+diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
+index 767a06ef68..f0fb022fc6 100644
+--- a/arch/arm/dts/stm32mp151.dtsi
++++ b/arch/arm/dts/stm32mp151.dtsi
+@@ -1143,10 +1143,9 @@
+ 			reg = <0x4c001000 0x400>;
+ 			st,proc-id = <0>;
+ 			interrupts-extended =
+-				<&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+-				<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+-				<&exti 61 1>;
+-			interrupt-names = "rx", "tx", "wakeup";
++				<&exti 61 1>,
++				<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "rx", "tx";
+ 			clocks = <&rcc IPCC>;
+ 			wakeup-source;
+ 			status = "disabled";
+diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi
+index 3d36cac9ed..5a045d7156 100644
+--- a/arch/arm/dts/stm32mp15xx-dkx.dtsi
++++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi
+@@ -685,6 +685,14 @@
+ &usbh_ehci {
+ 	phys = <&usbphyc_port0>;
+ 	status = "okay";
++	#address-cells = <1>;
++	#size-cells = <0>;
++	/* onboard HUB */
++	hub@1 {
++		compatible = "usb424,2514";
++		reg = <1>;
++		vdd-supply = <&v3v3>;
++	};
+ };
+ 
+ &usbotg_hs {
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0016-board-st-stm32mp1-use-of-correct-compatible-string-t.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0016-board-st-stm32mp1-use-of-correct-compatible-string-t.patch
new file mode 100644
index 00000000..87c77855
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0016-board-st-stm32mp1-use-of-correct-compatible-string-t.patch
@@ -0,0 +1,39 @@
+From 0e8b629a921d962ab02e726dbd1f3d2205612aae Mon Sep 17 00:00:00 2001
+From: Christophe Kerello <christophe.kerello@foss.st.com>
+Date: Mon, 12 Sep 2022 17:40:50 +0200
+Subject: [PATCH 016/117] board: st: stm32mp1: use of correct compatible string
+ to add partitions
+
+Current compatible string used to update SPI NAND and SPI NOR devices
+can lead to a wrong partitions update (for example, SPI NAND partitions
+added to SPI NOR node in the device tree). To avoid this wrong behavior,
+use jedec,spi-nor compatible string for SPI NOR devices and spi-nand
+compatible string for SPI NAND devices.
+
+[Backport of commit 89f3745152ab ("board: st: stm32mp1: use of correct compatible string to add partitions")]
+Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
+Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
+Change-Id: Ie91ed17082d9741d1dd9afe1f1d297ff7bcb6f69
+---
+ board/st/stm32mp1/stm32mp1.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
+index 8c162b42a5..7dc26f850f 100644
+--- a/board/st/stm32mp1/stm32mp1.c
++++ b/board/st/stm32mp1/stm32mp1.c
+@@ -898,8 +898,8 @@ int mmc_get_env_dev(void)
+ int ft_board_setup(void *blob, struct bd_info *bd)
+ {
+ 	static const struct node_info nodes[] = {
+-		{ "st,stm32f469-qspi",		MTD_DEV_TYPE_NOR,  },
+-		{ "st,stm32f469-qspi",		MTD_DEV_TYPE_SPINAND},
++		{ "jedec,spi-nor",		MTD_DEV_TYPE_NOR,  },
++		{ "spi-nand",			MTD_DEV_TYPE_SPINAND},
+ 		{ "st,stm32mp15-fmc2",		MTD_DEV_TYPE_NAND, },
+ 		{ "st,stm32mp1-fmc2-nfc",	MTD_DEV_TYPE_NAND, },
+ 	};
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0017-arm-stm32mp-add-defines-for-BSEC_LOCK-status-in-stm3.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0017-arm-stm32mp-add-defines-for-BSEC_LOCK-status-in-stm3.patch
new file mode 100644
index 00000000..3066d970
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0017-arm-stm32mp-add-defines-for-BSEC_LOCK-status-in-stm3.patch
@@ -0,0 +1,80 @@
+From 8b1eaf148b358bb4cb515f856b889e69977af657 Mon Sep 17 00:00:00 2001
+From: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Date: Thu, 15 Sep 2022 18:11:38 +0200
+Subject: [PATCH 017/117] arm: stm32mp: add defines for BSEC_LOCK status in
+ stm32key command
+
+Add defines for value used in stm32key for BSEC permanent lock status
+and error.
+
+This patch is a preliminary step to support more lock status in BSEC
+driver.
+
+[Backport of commit c6327ba40f59 ("arm: stm32mp: add defines for BSEC_LOCK status in stm32key command")]
+Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
+Change-Id: I69c1504bdbb53f1a937a2338105637a41f92ada8
+---
+ arch/arm/mach-stm32mp/cmd_stm32key.c | 15 +++++++++------
+ 1 file changed, 9 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c
+index 68f28922d1..1899d91ecb 100644
+--- a/arch/arm/mach-stm32mp/cmd_stm32key.c
++++ b/arch/arm/mach-stm32mp/cmd_stm32key.c
+@@ -19,6 +19,9 @@
+ #define STM32_OTP_HASH_KEY_START	24
+ #define STM32_OTP_HASH_KEY_SIZE		8
+ 
++#define BSEC_LOCK_ERROR			(-1)
++#define BSEC_LOCK_PERM			BIT(0)
++
+ static int get_misc_dev(struct udevice **dev)
+ {
+ 	int ret;
+@@ -60,14 +63,14 @@ static int read_hash_otp(bool print, bool *locked, bool *closed)
+ 			val = ~0x0;
+ 		ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4);
+ 		if (ret != 4)
+-			lock = -1;
++			lock = BSEC_LOCK_ERROR;
+ 		if (print)
+-			printf("OTP HASH %i: %x lock : %d\n", word, val, lock);
++			printf("OTP HASH %i: %x lock : %x\n", word, val, lock);
+ 		if (val == ~0x0)
+ 			nb_invalid++;
+ 		else if (val == 0x0)
+ 			nb_zero++;
+-		if (lock == 1)
++		if (lock & BSEC_LOCK_PERM)
+ 			nb_lock++;
+ 	}
+ 
+@@ -77,13 +80,13 @@ static int read_hash_otp(bool print, bool *locked, bool *closed)
+ 		val = 0x0;
+ 	ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4);
+ 	if (ret != 4)
+-		lock = -1;
++		lock = BSEC_LOCK_ERROR;
+ 
+ 	status = (val & STM32_OTP_CLOSE_MASK) == STM32_OTP_CLOSE_MASK;
+ 	if (closed)
+ 		*closed = status;
+ 	if (print)
+-		printf("OTP %d: closed status: %d lock : %d\n", word, status, lock);
++		printf("OTP %d: closed status: %d lock : %x\n", word, status, lock);
+ 
+ 	status = (nb_lock == STM32_OTP_HASH_KEY_SIZE);
+ 	if (locked)
+@@ -128,7 +131,7 @@ static int fuse_hash_value(u32 addr, bool print)
+ 			return ret;
+ 		}
+ 		/* on success, lock the OTP for HASH key */
+-		val = 1;
++		val = BSEC_LOCK_PERM;
+ 		ret = misc_write(dev, STM32_BSEC_LOCK(word), &val, 4);
+ 		if (ret != 4) {
+ 			log_err("Lock OTP %i failed\n", word);
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0022-ARM-dts-stm32mp15-update-DDR-node.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0022-ARM-dts-stm32mp15-update-DDR-node.patch
new file mode 100644
index 00000000..6c5b1a86
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0022-ARM-dts-stm32mp15-update-DDR-node.patch
@@ -0,0 +1,112 @@
+From fe451bd4a4c3c827b48ea55ff7e865e075b4c8ff Mon Sep 17 00:00:00 2001
+From: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Date: Wed, 21 Sep 2022 09:37:13 +0200
+Subject: [PATCH 022/117] ARM: dts: stm32mp15: update DDR node
+
+Remove the unnecessary nodes for TFABOOT and keep the mandatory part
+in SOC dtsi, only the DDRCTRL and DDRPHY addresses.
+This patch allows to manage the DDR configuration setting in U-Boot
+device tree only if it is needed, when CONFIG_SPL is defined.
+
+With TFABOOT, the DDR configuration is done in TF-A BL2 and the DDR size
+is dynamically computed in U-Boot since commit d72e7bbe7c28 ("ram:
+stm32mp1: compute DDR size from DDRCTL registers").
+
+[Backport of commit 9f7c58dc0dea ("ARM: dts: stm32mp15: update DDR node")]
+Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
+Change-Id: Id7d228115e1279043edd408b148df124acb5194c
+---
+ arch/arm/dts/stm32mp15-ddr.dtsi               | 16 ++++++++++++++++
+ arch/arm/dts/stm32mp15-u-boot.dtsi            | 14 --------------
+ arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi |  1 -
+ arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi |  1 -
+ 4 files changed, 16 insertions(+), 16 deletions(-)
+
+diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi
+index 0aac9131a6..d02f79dac6 100644
+--- a/arch/arm/dts/stm32mp15-ddr.dtsi
++++ b/arch/arm/dts/stm32mp15-ddr.dtsi
+@@ -4,7 +4,22 @@
+  */
+ #include <linux/stringify.h>
+ 
++#ifdef CONFIG_SPL
+ &ddr {
++	clocks = <&rcc AXIDCG>,
++		 <&rcc DDRC1>,
++		 <&rcc DDRC2>,
++		 <&rcc DDRPHYC>,
++		 <&rcc DDRCAPB>,
++		 <&rcc DDRPHYCAPB>;
++
++	clock-names = "axidcg",
++		      "ddrc1",
++		      "ddrc2",
++		      "ddrphyc",
++		      "ddrcapb",
++		      "ddrphycapb";
++
+ 	config-DDR_MEM_COMPATIBLE {
+ 		u-boot,dm-pre-reloc;
+ 
+@@ -119,6 +134,7 @@
+ 		status = "okay";
+ 	};
+ };
++#endif
+ 
+ #undef DDR_MEM_COMPATIBLE
+ #undef DDR_MEM_NAME
+diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi
+index d9d04743ac..d5c87d29d8 100644
+--- a/arch/arm/dts/stm32mp15-u-boot.dtsi
++++ b/arch/arm/dts/stm32mp15-u-boot.dtsi
+@@ -53,20 +53,6 @@
+ 			reg = <0x5a003000 0x550
+ 			       0x5a004000 0x234>;
+ 
+-			clocks = <&rcc AXIDCG>,
+-				 <&rcc DDRC1>,
+-				 <&rcc DDRC2>,
+-				 <&rcc DDRPHYC>,
+-				 <&rcc DDRCAPB>,
+-				 <&rcc DDRPHYCAPB>;
+-
+-			clock-names = "axidcg",
+-				      "ddrc1",
+-				      "ddrc2",
+-				      "ddrphyc",
+-				      "ddrcapb",
+-				      "ddrphycapb";
+-
+ 			status = "okay";
+ 		};
+ 	};
+diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
+index 2db045e7ce..1209dfe009 100644
+--- a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
++++ b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
+@@ -5,7 +5,6 @@
+ 
+ #include <dt-bindings/clock/stm32mp1-clksrc.h>
+ #include "stm32mp15-scmi-u-boot.dtsi"
+-#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
+ 
+ / {
+ 	aliases {
+diff --git a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
+index 54662f7e29..c265745ff1 100644
+--- a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
++++ b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
+@@ -5,7 +5,6 @@
+ 
+ #include <dt-bindings/clock/stm32mp1-clksrc.h>
+ #include "stm32mp15-scmi-u-boot.dtsi"
+-#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
+ 
+ / {
+ 	aliases {
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0042-ARM-dts-stm32-update-SCMI-dedicated-file.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0042-ARM-dts-stm32-update-SCMI-dedicated-file.patch
new file mode 100644
index 00000000..9f97e706
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0042-ARM-dts-stm32-update-SCMI-dedicated-file.patch
@@ -0,0 +1,35 @@
+From 70b703cfeb0f201698fcb71f5e23abf91f77f2a8 Mon Sep 17 00:00:00 2001
+From: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Date: Mon, 10 Oct 2022 10:56:14 +0200
+Subject: [PATCH 042/117] ARM: dts: stm32: update SCMI dedicated file
+
+The PWR regulators don't need be removed as they are already deactivated.
+This patches is a alignment with the accepted patch in Linux device tree
+in commit a34b42f8690c ("ARM: dts: stm32: fix pwr regulators references
+to use scmi").
+
+[Backport of commit 637a370251d3 ("ARM: dts: stm32: update SCMI dedicated file")]
+
+Fixes: 69ef98b209e7 ("ARM: dts: stm32mp15: alignment with v5.19")
+Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
+Change-Id: I172a7fb33d85edd7765bb1c3d61862c324047c29
+---
+ arch/arm/dts/stm32mp15-scmi.dtsi | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/arch/arm/dts/stm32mp15-scmi.dtsi b/arch/arm/dts/stm32mp15-scmi.dtsi
+index 37d4547b3e..543f24c2f4 100644
+--- a/arch/arm/dts/stm32mp15-scmi.dtsi
++++ b/arch/arm/dts/stm32mp15-scmi.dtsi
+@@ -103,7 +103,3 @@
+ /delete-node/ &clk_lse;
+ /delete-node/ &clk_lsi;
+ /delete-node/ &clk_csi;
+-/delete-node/ &reg11;
+-/delete-node/ &reg18;
+-/delete-node/ &usb33;
+-/delete-node/ &pwr_regulators;
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0053-ARM-dts-stm32-add-sdmmc-cd-gpios-for-STM32MP135F-DK.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0053-ARM-dts-stm32-add-sdmmc-cd-gpios-for-STM32MP135F-DK.patch
new file mode 100644
index 00000000..8520fe11
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0053-ARM-dts-stm32-add-sdmmc-cd-gpios-for-STM32MP135F-DK.patch
@@ -0,0 +1,37 @@
+From 0d9168bf5d464528daa8b0a36c5217843e21d650 Mon Sep 17 00:00:00 2001
+From: Yann Gautier <yann.gautier@foss.st.com>
+Date: Wed, 2 Nov 2022 14:53:48 +0100
+Subject: [PATCH 053/117] ARM: dts: stm32: add sdmmc cd-gpios for
+ STM32MP135F-DK
+
+On STM32MP135F-DK, the SD card detect GPIO is GPIOH4.
+Backport of the Linux patch:
+https://lore.kernel.org/linux-arm-kernel/20220921160334.3227138-1-yann.gautier@foss.st.com/
+
+[Backport of commit 3068bb60c6f7 ("ARM: dts: stm32: add sdmmc cd-gpios for STM32MP135F-DK")]
+
+Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
+Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
+Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
+Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Change-Id: I992b3ec68f9e7f99f0e4de4c90e57b52c4df7d53
+---
+ arch/arm/dts/stm32mp135f-dk.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts
+index e6b8ffd332..52f86596ce 100644
+--- a/arch/arm/dts/stm32mp135f-dk.dts
++++ b/arch/arm/dts/stm32mp135f-dk.dts
+@@ -82,7 +82,7 @@
+ 	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
+ 	pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>;
+ 	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+-	broken-cd;
++	cd-gpios = <&gpioh 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ 	disable-wp;
+ 	st,neg-edge;
+ 	bus-width = <4>;
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0063-dm-pmic-ignore-disabled-node-in-pmic_bind_children.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0063-dm-pmic-ignore-disabled-node-in-pmic_bind_children.patch
new file mode 100644
index 00000000..e09efb0e
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0063-dm-pmic-ignore-disabled-node-in-pmic_bind_children.patch
@@ -0,0 +1,41 @@
+From 67062a1a5467312c01d51957a3cc62631f8b5f51 Mon Sep 17 00:00:00 2001
+From: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Date: Wed, 26 Oct 2022 15:05:10 +0200
+Subject: [PATCH 063/117] dm: pmic: ignore disabled node in pmic_bind_children
+
+Ignore the disabled children node in pmic_bind_children() so the
+disabled regulators in device tree are not registered.
+
+This patch is based on the dm_scan_fdt_node() code - only the
+activated nodes are bound -  and it solves possible issue when a
+deactivated regulator is bound, error for duplicated regulator name
+for example.
+
+[Backport of commit 30257f4699e0 ("dm: pmic: ignore disabled
+ node in pmic_bind_children")]
+
+Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Reviewed-by: Simon Glass <sjg@chromium.org>
+Change-Id: I8e4ec033a389c434c6ab892a5b2f7ee64a8ce0bf
+---
+ drivers/power/pmic/pmic-uclass.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/power/pmic/pmic-uclass.c b/drivers/power/pmic/pmic-uclass.c
+index 5dcf6d8079..0e2f5e1f41 100644
+--- a/drivers/power/pmic/pmic-uclass.c
++++ b/drivers/power/pmic/pmic-uclass.c
+@@ -39,6 +39,10 @@ int pmic_bind_children(struct udevice *pmic, ofnode parent,
+ 		node_name = ofnode_get_name(node);
+ 
+ 		debug("* Found child node: '%s'\n", node_name);
++		if (!ofnode_is_enabled(node)) {
++			debug("  - ignoring disabled device\n");
++			continue;
++		}
+ 
+ 		child = NULL;
+ 		for (info = child_info; info->prefix && info->driver; info++) {
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0069-tee-optee-don-t-fail-probe-because-of-optee-rng.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0069-tee-optee-don-t-fail-probe-because-of-optee-rng.patch
new file mode 100644
index 00000000..8df54cf5
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0069-tee-optee-don-t-fail-probe-because-of-optee-rng.patch
@@ -0,0 +1,37 @@
+From 9c5e59f304c49059398977ebd8e322ffa128b28a Mon Sep 17 00:00:00 2001
+From: Etienne Carriere <etienne.carriere@linaro.org>
+Date: Wed, 7 Dec 2022 16:29:59 +0100
+Subject: [PATCH 069/117] tee: optee: don't fail probe because of optee-rng
+
+Fixes optee-rng driver bind sequence in optee driver to print a warning
+message but not report an error status when a optee-rng service driver
+fails to be bound as the optee driver itself is still fully functional.
+
+[Backport of commit 476a3d58dfeb ("tee: optee: don't fail probe because
+ of optee-rng")
+
+Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
+Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
+Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
+Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
+Change-Id: I54e9a734316c963f5b93382fe2f0d3b4efa7c2ae
+---
+ drivers/tee/optee/core.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c
+index 9240277579..604fd1414f 100644
+--- a/drivers/tee/optee/core.c
++++ b/drivers/tee/optee/core.c
+@@ -834,7 +834,7 @@ static int optee_probe(struct udevice *dev)
+ 		 */
+ 		ret = device_bind_driver(dev, "optee-rng", "optee-rng", NULL);
+ 		if (ret)
+-			return ret;
++			dev_warn(dev, "ftpm_tee failed to bind: %d\n", ret);
+ 	}
+ 
+ 	return 0;
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0070-tee-optee-discover-services-dependent-on-tee-supplic.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0070-tee-optee-discover-services-dependent-on-tee-supplic.patch
new file mode 100644
index 00000000..ddf7437c
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0070-tee-optee-discover-services-dependent-on-tee-supplic.patch
@@ -0,0 +1,116 @@
+From 616941daae3a24b41c309651485546c7dc79667d Mon Sep 17 00:00:00 2001
+From: Etienne Carriere <etienne.carriere@linaro.org>
+Date: Wed, 7 Dec 2022 16:30:00 +0100
+Subject: [PATCH 070/117] tee: optee: discover services dependent on
+ tee-supplicant
+
+Makes OP-TEE to enumerate also services depending on tee-supplicant
+support in U-Boot. This change allows OP-TEE services like fTPM TA
+to be discovered and get a TPM device registered in U-Boot.
+
+[Backport of commit fe8a4ed01110 ("tee: optee: discover services
+ dependent on tee-supplicant")]
+
+Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
+Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
+Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
+Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
+Change-Id: I08861a4be342543323aafe81325742c58a4f4069
+---
+ drivers/tee/optee/core.c | 32 +++++++++++++++++++++++---------
+ 1 file changed, 23 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c
+index 604fd1414f..b21031d7d8 100644
+--- a/drivers/tee/optee/core.c
++++ b/drivers/tee/optee/core.c
+@@ -102,13 +102,14 @@ static int bind_service_list(struct udevice *dev, struct tee_shm *service_list,
+ 	return 0;
+ }
+ 
+-static int __enum_services(struct udevice *dev, struct tee_shm *shm, size_t *shm_size, u32 tee_sess)
++static int __enum_services(struct udevice *dev, struct tee_shm *shm, size_t *shm_size, u32 tee_sess,
++			   unsigned int pta_cmd)
+ {
+ 	struct tee_invoke_arg arg = { };
+ 	struct tee_param param = { };
+ 	int ret = 0;
+ 
+-	arg.func = PTA_CMD_GET_DEVICES;
++	arg.func = pta_cmd;
+ 	arg.session = tee_sess;
+ 
+ 	/* Fill invoke cmd params */
+@@ -118,7 +119,7 @@ static int __enum_services(struct udevice *dev, struct tee_shm *shm, size_t *shm
+ 
+ 	ret = tee_invoke_func(dev, &arg, 1, &param);
+ 	if (ret || (arg.ret && arg.ret != TEE_ERROR_SHORT_BUFFER)) {
+-		dev_err(dev, "PTA_CMD_GET_DEVICES invoke function err: 0x%x\n", arg.ret);
++		dev_err(dev, "Enumeration command 0x%x failed: 0x%x\n", pta_cmd, arg.ret);
+ 		return -EINVAL;
+ 	}
+ 
+@@ -127,12 +128,13 @@ static int __enum_services(struct udevice *dev, struct tee_shm *shm, size_t *shm
+ 	return 0;
+ }
+ 
+-static int enum_services(struct udevice *dev, struct tee_shm **shm, size_t *count, u32 tee_sess)
++static int enum_services(struct udevice *dev, struct tee_shm **shm, size_t *count, u32 tee_sess,
++			 unsigned int pta_cmd)
+ {
+ 	size_t shm_size = 0;
+ 	int ret;
+ 
+-	ret = __enum_services(dev, NULL, &shm_size, tee_sess);
++	ret = __enum_services(dev, NULL, &shm_size, tee_sess, pta_cmd);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -142,7 +144,7 @@ static int enum_services(struct udevice *dev, struct tee_shm **shm, size_t *coun
+ 		return ret;
+ 	}
+ 
+-	ret = __enum_services(dev, *shm, &shm_size, tee_sess);
++	ret = __enum_services(dev, *shm, &shm_size, tee_sess, pta_cmd);
+ 	if (!ret)
+ 		*count = shm_size / sizeof(struct tee_optee_ta_uuid);
+ 
+@@ -174,20 +176,32 @@ static int bind_service_drivers(struct udevice *dev)
+ 	struct tee_shm *service_list = NULL;
+ 	size_t service_count;
+ 	u32 tee_sess;
+-	int ret;
++	int ret, ret2;
+ 
+ 	ret = open_enum_session(dev, &tee_sess);
+ 	if (ret)
+ 		return ret;
+ 
+-	ret = enum_services(dev, &service_list, &service_count, tee_sess);
++	ret = enum_services(dev, &service_list, &service_count, tee_sess,
++			    PTA_CMD_GET_DEVICES);
+ 	if (!ret)
+ 		ret = bind_service_list(dev, service_list, service_count);
+ 
+ 	tee_shm_free(service_list);
++
++	ret2 = enum_services(dev, &service_list, &service_count, tee_sess,
++			     PTA_CMD_GET_DEVICES_SUPP);
++	if (!ret2)
++		ret2 = bind_service_list(dev, service_list, service_count);
++
++	tee_shm_free(service_list);
++
+ 	tee_close_session(dev, tee_sess);
+ 
+-	return ret;
++	if (ret)
++		return ret;
++
++	return ret2;
+ }
+ 
+ /**
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0071-optee-bind-the-TA-drivers-on-OP-TEE-node.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0071-optee-bind-the-TA-drivers-on-OP-TEE-node.patch
new file mode 100644
index 00000000..d02b183f
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0071-optee-bind-the-TA-drivers-on-OP-TEE-node.patch
@@ -0,0 +1,68 @@
+From 6f8c1e8732a95edc08090fce4b33e11cb6be8dbb Mon Sep 17 00:00:00 2001
+From: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Date: Thu, 15 Dec 2022 09:54:52 +0100
+Subject: [PATCH 071/117] optee: bind the TA drivers on OP-TEE node
+
+In U-Boot driver model the devices can be referenced by
+phandle in the U-Boot configuration nodes.
+
+Without a valid node provided during the bind, the driver
+associated to OP-TEE TA can't be referenced.
+
+For example to force the sequence number with alias
+(.flags = DM_UC_FLAG_SEQ_ALIAS)
+
+ 	aliases {
+		rng0 = &optee;
+ 	};
+
+or other configuration:
+
+board-sysinfo {
+   compatible = "vendor,sysinfo-board";
+   ramdom = <&optee>;
+}
+
+With this patch all drivers bound from OP-TEE service
+discovery are now associated are associated to OP-TEE
+node, allowing to identify by phandle the driver
+provided by the TA for one UCLASS without modifying
+device tree.
+
+[Backport of commit 59dacc319030 ("optee: bind the TA drivers on
+ OP-TEE node")]
+
+Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
+Change-Id: Id817640551f8c4b56cdf7a73995b18d7293b14fa
+---
+ drivers/tee/optee/core.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c
+index b21031d7d8..a813a84a4f 100644
+--- a/drivers/tee/optee/core.c
++++ b/drivers/tee/optee/core.c
+@@ -92,7 +92,8 @@ static int bind_service_list(struct udevice *dev, struct tee_shm *service_list,
+ 		if (!service)
+ 			continue;
+ 
+-		ret = device_bind_driver(dev, service->driver_name, service->driver_name, NULL);
++		ret = device_bind_driver_to_node(dev, service->driver_name, service->driver_name,
++						 dev_ofnode(dev), NULL);
+ 		if (ret) {
+ 			dev_warn(dev, "%s was not bound: %d, ignored\n", service->driver_name, ret);
+ 			continue;
+@@ -846,7 +847,8 @@ static int optee_probe(struct udevice *dev)
+ 		 * Discovery of TAs on the TEE bus is not supported in U-Boot:
+ 		 * only bind the drivers associated to the supported OP-TEE TA
+ 		 */
+-		ret = device_bind_driver(dev, "optee-rng", "optee-rng", NULL);
++		ret = device_bind_driver_to_node(dev, "optee-rng", "optee-rng",
++						 dev_ofnode(dev), NULL);
+ 		if (ret)
+ 			dev_warn(dev, "ftpm_tee failed to bind: %d\n", ret);
+ 	}
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0081-ARM-dts-stm32mp15-remove-clksrc-include-in-SCMI-dtsi.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0081-ARM-dts-stm32mp15-remove-clksrc-include-in-SCMI-dtsi.patch
new file mode 100644
index 00000000..95792d6e
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0081-ARM-dts-stm32mp15-remove-clksrc-include-in-SCMI-dtsi.patch
@@ -0,0 +1,50 @@
+From fc0d71a5af1a796355026a5fbc090bbb564fdabb Mon Sep 17 00:00:00 2001
+From: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Date: Wed, 14 Dec 2022 16:24:59 +0100
+Subject: [PATCH 081/117] ARM: dts: stm32mp15: remove clksrc include in SCMI
+ dtsi file
+
+The include file stm32mp1-clksrc.h is not necessary for the SCMI STM32MP15
+dtsi files as the clock tree is not defined in the U-Boot SCMI device tree;
+these SCMI device tree only support TFABOOT with stm32mp15_defconfig,
+SPL with the basic boot defconfig is not supported.
+
+[Backport of commit d1d56638c4e8 ("ARM: dts: stm32mp15: remove clksrc
+ include in SCMI dtsi file")]
+
+Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
+Change-Id: Ib96329f23b27691d7a9c091a6a88be2658143ddc
+Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/270203
+---
+ arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi | 1 -
+ arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi | 1 -
+ 2 files changed, 2 deletions(-)
+
+diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
+index 1209dfe009..92fdf09872 100644
+--- a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
++++ b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
+@@ -3,7 +3,6 @@
+  * Copyright : STMicroelectronics 2022
+  */
+ 
+-#include <dt-bindings/clock/stm32mp1-clksrc.h>
+ #include "stm32mp15-scmi-u-boot.dtsi"
+ 
+ / {
+diff --git a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
+index c265745ff1..63948ef493 100644
+--- a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
++++ b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
+@@ -3,7 +3,6 @@
+  * Copyright : STMicroelectronics 2022
+  */
+ 
+-#include <dt-bindings/clock/stm32mp1-clksrc.h>
+ #include "stm32mp15-scmi-u-boot.dtsi"
+ 
+ / {
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0083-ARM-dts-stm32-Add-timer-interrupts-on-stm32mp15.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0083-ARM-dts-stm32-Add-timer-interrupts-on-stm32mp15.patch
new file mode 100644
index 00000000..902bb75c
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0083-ARM-dts-stm32-Add-timer-interrupts-on-stm32mp15.patch
@@ -0,0 +1,162 @@
+From 13903278e75fa011f46e53aeaca05bf42a7119e9 Mon Sep 17 00:00:00 2001
+From: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Date: Wed, 14 Dec 2022 16:25:01 +0100
+Subject: [PATCH 083/117] ARM: dts: stm32: Add timer interrupts on stm32mp15
+
+The timer units in the stm32mp15x CPUs have interrupts, depending on the
+timer flavour either one "global" or four dedicated ones. Add the irqs
+to the timer units on stm32mp15x.
+
+Sync the DT Files with linux kernel v6.1 and with commit a9b70102253ce
+("ARM: dts: stm32: Add timer interrupts on stm32mp15")
+
+[Backport of commit 6e391c7d5f36 ("ARM: dts: stm32: Add timer interrupts
+ on stm32mp15")]
+
+Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
+Change-Id: I55c811a8c5e305f772dac7f0337e23d37143c36a
+Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/277243
+---
+ arch/arm/dts/stm32mp151.dtsi | 34 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 34 insertions(+)
+
+diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
+index 8bbb1aef2e..5d178b5d3c 100644
+--- a/arch/arm/dts/stm32mp151.dtsi
++++ b/arch/arm/dts/stm32mp151.dtsi
+@@ -145,6 +145,8 @@
+ 			#size-cells = <0>;
+ 			compatible = "st,stm32-timers";
+ 			reg = <0x40000000 0x400>;
++			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "global";
+ 			clocks = <&rcc TIM2_K>;
+ 			clock-names = "int";
+ 			dmas = <&dmamux1 18 0x400 0x1>,
+@@ -178,6 +180,8 @@
+ 			#size-cells = <0>;
+ 			compatible = "st,stm32-timers";
+ 			reg = <0x40001000 0x400>;
++			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "global";
+ 			clocks = <&rcc TIM3_K>;
+ 			clock-names = "int";
+ 			dmas = <&dmamux1 23 0x400 0x1>,
+@@ -212,6 +216,8 @@
+ 			#size-cells = <0>;
+ 			compatible = "st,stm32-timers";
+ 			reg = <0x40002000 0x400>;
++			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "global";
+ 			clocks = <&rcc TIM4_K>;
+ 			clock-names = "int";
+ 			dmas = <&dmamux1 29 0x400 0x1>,
+@@ -244,6 +250,8 @@
+ 			#size-cells = <0>;
+ 			compatible = "st,stm32-timers";
+ 			reg = <0x40003000 0x400>;
++			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "global";
+ 			clocks = <&rcc TIM5_K>;
+ 			clock-names = "int";
+ 			dmas = <&dmamux1 55 0x400 0x1>,
+@@ -278,6 +286,8 @@
+ 			#size-cells = <0>;
+ 			compatible = "st,stm32-timers";
+ 			reg = <0x40004000 0x400>;
++			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "global";
+ 			clocks = <&rcc TIM6_K>;
+ 			clock-names = "int";
+ 			dmas = <&dmamux1 69 0x400 0x1>;
+@@ -296,6 +306,8 @@
+ 			#size-cells = <0>;
+ 			compatible = "st,stm32-timers";
+ 			reg = <0x40005000 0x400>;
++			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "global";
+ 			clocks = <&rcc TIM7_K>;
+ 			clock-names = "int";
+ 			dmas = <&dmamux1 70 0x400 0x1>;
+@@ -314,6 +326,8 @@
+ 			#size-cells = <0>;
+ 			compatible = "st,stm32-timers";
+ 			reg = <0x40006000 0x400>;
++			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "global";
+ 			clocks = <&rcc TIM12_K>;
+ 			clock-names = "int";
+ 			status = "disabled";
+@@ -336,6 +350,8 @@
+ 			#size-cells = <0>;
+ 			compatible = "st,stm32-timers";
+ 			reg = <0x40007000 0x400>;
++			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "global";
+ 			clocks = <&rcc TIM13_K>;
+ 			clock-names = "int";
+ 			status = "disabled";
+@@ -358,6 +374,8 @@
+ 			#size-cells = <0>;
+ 			compatible = "st,stm32-timers";
+ 			reg = <0x40008000 0x400>;
++			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "global";
+ 			clocks = <&rcc TIM14_K>;
+ 			clock-names = "int";
+ 			status = "disabled";
+@@ -641,6 +659,11 @@
+ 			#size-cells = <0>;
+ 			compatible = "st,stm32-timers";
+ 			reg = <0x44000000 0x400>;
++			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "brk", "up", "trg-com", "cc";
+ 			clocks = <&rcc TIM1_K>;
+ 			clock-names = "int";
+ 			dmas = <&dmamux1 11 0x400 0x1>,
+@@ -677,6 +700,11 @@
+ 			#size-cells = <0>;
+ 			compatible = "st,stm32-timers";
+ 			reg = <0x44001000 0x400>;
++			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "brk", "up", "trg-com", "cc";
+ 			clocks = <&rcc TIM8_K>;
+ 			clock-names = "int";
+ 			dmas = <&dmamux1 47 0x400 0x1>,
+@@ -764,6 +792,8 @@
+ 			#size-cells = <0>;
+ 			compatible = "st,stm32-timers";
+ 			reg = <0x44006000 0x400>;
++			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "global";
+ 			clocks = <&rcc TIM15_K>;
+ 			clock-names = "int";
+ 			dmas = <&dmamux1 105 0x400 0x1>,
+@@ -791,6 +821,8 @@
+ 			#size-cells = <0>;
+ 			compatible = "st,stm32-timers";
+ 			reg = <0x44007000 0x400>;
++			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "global";
+ 			clocks = <&rcc TIM16_K>;
+ 			clock-names = "int";
+ 			dmas = <&dmamux1 109 0x400 0x1>,
+@@ -815,6 +847,8 @@
+ 			#size-cells = <0>;
+ 			compatible = "st,stm32-timers";
+ 			reg = <0x44008000 0x400>;
++			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "global";
+ 			clocks = <&rcc TIM17_K>;
+ 			clock-names = "int";
+ 			dmas = <&dmamux1 111 0x400 0x1>,
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0084-stm32mp-cosmetic-Update-of-bsec-driver.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0084-stm32mp-cosmetic-Update-of-bsec-driver.patch
new file mode 100644
index 00000000..372d3f80
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0084-stm32mp-cosmetic-Update-of-bsec-driver.patch
@@ -0,0 +1,43 @@
+From 5c7db126ee416e30469729d37ab0df4536cd6919 Mon Sep 17 00:00:00 2001
+From: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Date: Fri, 6 Jan 2023 13:20:14 +0100
+Subject: [PATCH 084/117] stm32mp: cosmetic: Update of bsec driver
+
+Remove unnecessary return in stm32mp_bsec_write_lock and replace tab
+by space for plat_auto opts.
+
+[Backport of commit 27bad4e7fcb1 ("stm32mp: cosmetic: Update of bsec
+ driver")]
+
+Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
+Change-Id: Ic26b0ca7844f97c9e2b87c6e403985205a05bc0f
+---
+ arch/arm/mach-stm32mp/bsec.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c
+index c00130b08b..51ccff9aa5 100644
+--- a/arch/arm/mach-stm32mp/bsec.c
++++ b/arch/arm/mach-stm32mp/bsec.c
+@@ -468,8 +468,6 @@ static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp)
+ 	plat = dev_get_plat(dev);
+ 
+ 	return bsec_permanent_lock_otp(dev, plat->base, otp);
+-
+-	return -EINVAL;
+ }
+ 
+ static int stm32mp_bsec_read(struct udevice *dev, int offset,
+@@ -608,7 +606,7 @@ U_BOOT_DRIVER(stm32mp_bsec) = {
+ 	.id = UCLASS_MISC,
+ 	.of_match = stm32mp_bsec_ids,
+ 	.of_to_plat = stm32mp_bsec_of_to_plat,
+-	.plat_auto	= sizeof(struct stm32mp_bsec_plat),
++	.plat_auto = sizeof(struct stm32mp_bsec_plat),
+ 	.ops = &stm32mp_bsec_ops,
+ 	.probe = stm32mp_bsec_probe,
+ };
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0085-stm32mp-Add-OP-TEE-support-in-bsec-driver.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0085-stm32mp-Add-OP-TEE-support-in-bsec-driver.patch
new file mode 100644
index 00000000..c0b67cc9
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0085-stm32mp-Add-OP-TEE-support-in-bsec-driver.patch
@@ -0,0 +1,383 @@
+From a4cfe26f1bbe64c971a06462fa7e348ea8d530b9 Mon Sep 17 00:00:00 2001
+From: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Date: Fri, 6 Jan 2023 13:20:15 +0100
+Subject: [PATCH 085/117] stm32mp: Add OP-TEE support in bsec driver
+
+When OP-TEE is used, the SMC for BSEC management are not available and
+the STM32MP BSEC pseudo TA must be used (it is mandatory for STM32MP13
+and it is a new feature for STM32MP15x).
+
+The BSEC driver try to open a session to this PTA BSEC at probe
+and use it for OTP read or write access to fuse or to shadow.
+
+This patch also adapts the commands stm32key and stboard to handle
+the BSEC_LOCK_PERM lock value instead of 1.
+
+[Backport of commit 33a909a42a07 ("stm32mp: Add OP-TEE support in bsec
+ driver")]
+
+Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
+Change-Id: I1ce5f38d7d31c1cf1429ca1b29ef202a1f5b78c6
+Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/270215
+---
+ arch/arm/mach-stm32mp/bsec.c              | 173 +++++++++++++++++++++-
+ arch/arm/mach-stm32mp/cmd_stm32key.c      |   4 +-
+ arch/arm/mach-stm32mp/include/mach/bsec.h |   7 +
+ board/st/common/cmd_stboard.c             |   5 +-
+ doc/board/st/stm32mp1.rst                 |   6 +-
+ 5 files changed, 183 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c
+index 51ccff9aa5..fe79c986f9 100644
+--- a/arch/arm/mach-stm32mp/bsec.c
++++ b/arch/arm/mach-stm32mp/bsec.c
+@@ -10,9 +10,11 @@
+ #include <dm.h>
+ #include <log.h>
+ #include <misc.h>
++#include <tee.h>
+ #include <asm/io.h>
+ #include <asm/arch/bsec.h>
+ #include <asm/arch/stm32mp1_smc.h>
++#include <dm/device.h>
+ #include <dm/device_compat.h>
+ #include <linux/arm-smccc.h>
+ #include <linux/iopoll.h>
+@@ -63,10 +65,43 @@
+  */
+ #define BSEC_LOCK_PROGRAM		0x04
+ 
++#define PTA_BSEC_UUID { 0x94cf71ad, 0x80e6, 0x40b5, \
++	{ 0xa7, 0xc6, 0x3d, 0xc5, 0x01, 0xeb, 0x28, 0x03 } }
++
++/*
++ * Read OTP memory
++ *
++ * [in]		value[0].a		OTP start offset in byte
++ * [in]		value[0].b		Access type (0:shadow, 1:fuse, 2:lock)
++ * [out]	memref[1].buffer	Output buffer to store read values
++ * [out]	memref[1].size		Size of OTP to be read
++ *
++ * Return codes:
++ * TEE_SUCCESS - Invoke command success
++ * TEE_ERROR_BAD_PARAMETERS - Incorrect input param
++ * TEE_ERROR_ACCESS_DENIED - OTP not accessible by caller
++ */
++#define PTA_BSEC_READ_MEM		0x0
++
+ /*
+- * OTP status: bit 0 permanent lock
++ * Write OTP memory
++ *
++ * [in]		value[0].a		OTP start offset in byte
++ * [in]		value[0].b		Access type (0:shadow, 1:fuse, 2:lock)
++ * [in]		memref[1].buffer	Input buffer to read values
++ * [in]		memref[1].size		Size of OTP to be written
++ *
++ * Return codes:
++ * TEE_SUCCESS - Invoke command success
++ * TEE_ERROR_BAD_PARAMETERS - Incorrect input param
++ * TEE_ERROR_ACCESS_DENIED - OTP not accessible by caller
+  */
+-#define BSEC_LOCK_PERM			BIT(0)
++#define PTA_BSEC_WRITE_MEM		0x1
++
++/* value of PTA_BSEC access type = value[in] b */
++#define SHADOW_ACCESS			0
++#define FUSE_ACCESS			1
++#define LOCK_ACCESS			2
+ 
+ /**
+  * bsec_lock() - manage lock for each type SR/SP/SW
+@@ -359,6 +394,10 @@ struct stm32mp_bsec_plat {
+ 	u32 base;
+ };
+ 
++struct stm32mp_bsec_priv {
++	struct udevice *tee;
++};
++
+ static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp)
+ {
+ 	struct stm32mp_bsec_plat *plat;
+@@ -470,14 +509,109 @@ static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp)
+ 	return bsec_permanent_lock_otp(dev, plat->base, otp);
+ }
+ 
++static int bsec_pta_open_session(struct udevice *tee, u32 *tee_session)
++{
++	const struct tee_optee_ta_uuid uuid = PTA_BSEC_UUID;
++	struct tee_open_session_arg arg;
++	int rc;
++
++	memset(&arg, 0, sizeof(arg));
++	tee_optee_ta_uuid_to_octets(arg.uuid, &uuid);
++	arg.clnt_login = TEE_LOGIN_REE_KERNEL;
++	rc = tee_open_session(tee, &arg, 0, NULL);
++	if (rc < 0)
++		return -ENODEV;
++
++	*tee_session = arg.session;
++
++	return 0;
++}
++
++static int bsec_optee_open(struct udevice *dev)
++{
++	struct stm32mp_bsec_priv *priv = dev_get_priv(dev);
++	struct udevice *tee;
++	u32 tee_session;
++	int rc;
++
++	tee = tee_find_device(NULL, NULL, NULL, NULL);
++	if (!tee)
++		return -ENODEV;
++
++	/* try to open the STM32 BSEC TA */
++	rc = bsec_pta_open_session(tee, &tee_session);
++	if (rc)
++		return rc;
++
++	tee_close_session(tee, tee_session);
++
++	priv->tee = tee;
++
++	return 0;
++}
++
++static int bsec_optee_pta(struct udevice *dev, int cmd, int type, int offset,
++			  void *buff, ulong size)
++{
++	struct stm32mp_bsec_priv *priv = dev_get_priv(dev);
++	u32 tee_session;
++	struct tee_invoke_arg arg;
++	struct tee_param param[2];
++	struct tee_shm *fw_shm;
++	int rc;
++
++	rc = bsec_pta_open_session(priv->tee, &tee_session);
++	if (rc)
++		return rc;
++
++	rc = tee_shm_register(priv->tee, buff, size, 0, &fw_shm);
++	if (rc)
++		goto close_session;
++
++	memset(&arg, 0, sizeof(arg));
++	arg.func = cmd;
++	arg.session = tee_session;
++
++	memset(param, 0, sizeof(param));
++
++	param[0].attr = TEE_PARAM_ATTR_TYPE_VALUE_INPUT;
++	param[0].u.value.a = offset;
++	param[0].u.value.b = type;
++
++	if (cmd == PTA_BSEC_WRITE_MEM)
++		param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT;
++	else
++		param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_OUTPUT;
++
++	param[1].u.memref.shm = fw_shm;
++	param[1].u.memref.size = size;
++
++	rc = tee_invoke_func(priv->tee, &arg, 2, param);
++	if (rc < 0 || arg.ret != 0) {
++		dev_err(priv->tee,
++			"PTA_BSEC invoke failed TEE err: %x, err:%x\n",
++			arg.ret, rc);
++		if (!rc)
++			rc = -EIO;
++	}
++
++	tee_shm_free(fw_shm);
++
++close_session:
++	tee_close_session(priv->tee, tee_session);
++
++	return rc;
++}
++
+ static int stm32mp_bsec_read(struct udevice *dev, int offset,
+ 			     void *buf, int size)
+ {
++	struct stm32mp_bsec_priv *priv = dev_get_priv(dev);
+ 	int ret;
+ 	int i;
+ 	bool shadow = true, lock = false;
+ 	int nb_otp = size / sizeof(u32);
+-	int otp;
++	int otp, cmd;
+ 	unsigned int offs = offset;
+ 
+ 	if (offs >= STM32_BSEC_LOCK_OFFSET) {
+@@ -491,6 +625,19 @@ static int stm32mp_bsec_read(struct udevice *dev, int offset,
+ 	if ((offs % 4) || (size % 4))
+ 		return -EINVAL;
+ 
++	if (IS_ENABLED(CONFIG_OPTEE) && priv->tee) {
++		cmd = FUSE_ACCESS;
++		if (shadow)
++			cmd = SHADOW_ACCESS;
++		if (lock)
++			cmd = LOCK_ACCESS;
++		ret = bsec_optee_pta(dev, PTA_BSEC_READ_MEM, cmd, offs, buf, size);
++		if (ret)
++			return ret;
++
++		return size;
++	}
++
+ 	otp = offs / sizeof(u32);
+ 
+ 	for (i = otp; i < (otp + nb_otp) && i <= BSEC_OTP_MAX_VALUE; i++) {
+@@ -515,11 +662,12 @@ static int stm32mp_bsec_read(struct udevice *dev, int offset,
+ static int stm32mp_bsec_write(struct udevice *dev, int offset,
+ 			      const void *buf, int size)
+ {
++	struct stm32mp_bsec_priv *priv = dev_get_priv(dev);
+ 	int ret = 0;
+ 	int i;
+ 	bool shadow = true, lock = false;
+ 	int nb_otp = size / sizeof(u32);
+-	int otp;
++	int otp, cmd;
+ 	unsigned int offs = offset;
+ 
+ 	if (offs >= STM32_BSEC_LOCK_OFFSET) {
+@@ -533,6 +681,19 @@ static int stm32mp_bsec_write(struct udevice *dev, int offset,
+ 	if ((offs % 4) || (size % 4))
+ 		return -EINVAL;
+ 
++	if (IS_ENABLED(CONFIG_OPTEE) && priv->tee) {
++		cmd = FUSE_ACCESS;
++		if (shadow)
++			cmd = SHADOW_ACCESS;
++		if (lock)
++			cmd = LOCK_ACCESS;
++		ret = bsec_optee_pta(dev, PTA_BSEC_WRITE_MEM, cmd, offs, (void *)buf, size);
++		if (ret)
++			return ret;
++
++		return size;
++	}
++
+ 	otp = offs / sizeof(u32);
+ 
+ 	for (i = otp; i < otp + nb_otp && i <= BSEC_OTP_MAX_VALUE; i++) {
+@@ -581,6 +742,9 @@ static int stm32mp_bsec_probe(struct udevice *dev)
+ 			return ret;
+ 	}
+ 
++	if (IS_ENABLED(CONFIG_OPTEE))
++		bsec_optee_open(dev);
++
+ 	/*
+ 	 * update unlocked shadow for OTP cleared by the rom code
+ 	 * only executed in SPL, it is done in TF-A for TFABOOT
+@@ -607,6 +771,7 @@ U_BOOT_DRIVER(stm32mp_bsec) = {
+ 	.of_match = stm32mp_bsec_ids,
+ 	.of_to_plat = stm32mp_bsec_of_to_plat,
+ 	.plat_auto = sizeof(struct stm32mp_bsec_plat),
++	.priv_auto = sizeof(struct stm32mp_bsec_priv),
+ 	.ops = &stm32mp_bsec_ops,
+ 	.probe = stm32mp_bsec_probe,
+ };
+diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c
+index 278253e472..85be8e23bd 100644
+--- a/arch/arm/mach-stm32mp/cmd_stm32key.c
++++ b/arch/arm/mach-stm32mp/cmd_stm32key.c
+@@ -8,6 +8,7 @@
+ #include <console.h>
+ #include <log.h>
+ #include <misc.h>
++#include <asm/arch/bsec.h>
+ #include <dm/device.h>
+ #include <dm/uclass.h>
+ 
+@@ -84,9 +85,6 @@ static u32 get_otp_close_mask(void)
+ 		return STM32_OTP_STM32MP15x_CLOSE_MASK;
+ }
+ 
+-#define BSEC_LOCK_ERROR			(-1)
+-#define BSEC_LOCK_PERM			BIT(0)
+-
+ static int get_misc_dev(struct udevice **dev)
+ {
+ 	int ret;
+diff --git a/arch/arm/mach-stm32mp/include/mach/bsec.h b/arch/arm/mach-stm32mp/include/mach/bsec.h
+index 252eac3946..10ebc535c4 100644
+--- a/arch/arm/mach-stm32mp/include/mach/bsec.h
++++ b/arch/arm/mach-stm32mp/include/mach/bsec.h
+@@ -5,3 +5,10 @@
+ 
+ /* check self hosted debug status = BSEC_DENABLE.DBGSWENABLE */
+ bool bsec_dbgswenable(void);
++
++/* Bitfield definition for LOCK status */
++#define BSEC_LOCK_PERM			BIT(30)
++#define BSEC_LOCK_SHADOW_R		BIT(29)
++#define BSEC_LOCK_SHADOW_W		BIT(28)
++#define BSEC_LOCK_SHADOW_P		BIT(27)
++#define BSEC_LOCK_ERROR			BIT(26)
+diff --git a/board/st/common/cmd_stboard.c b/board/st/common/cmd_stboard.c
+index e12669b862..213fb5d302 100644
+--- a/board/st/common/cmd_stboard.c
++++ b/board/st/common/cmd_stboard.c
+@@ -34,6 +34,7 @@
+ #include <command.h>
+ #include <console.h>
+ #include <misc.h>
++#include <asm/arch/bsec.h>
+ #include <dm/device.h>
+ #include <dm/uclass.h>
+ 
+@@ -109,7 +110,7 @@ static int do_stboard(struct cmd_tbl *cmdtp, int flag, int argc,
+ 		else
+ 			display_stboard(otp);
+ 		printf("      OTP %d %s locked !\n", BSEC_OTP_BOARD,
+-		       lock == 1 ? "" : "NOT");
++		       lock & BSEC_LOCK_PERM ? "" : "NOT");
+ 		return CMD_RET_SUCCESS;
+ 	}
+ 
+@@ -178,7 +179,7 @@ static int do_stboard(struct cmd_tbl *cmdtp, int flag, int argc,
+ 	}
+ 
+ 	/* write persistent lock */
+-	otp = 1;
++	otp = BSEC_LOCK_PERM;
+ 	ret = misc_write(dev, STM32_BSEC_LOCK(BSEC_OTP_BOARD),
+ 			 &otp, sizeof(otp));
+ 	if (ret != sizeof(otp)) {
+diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst
+index 3759df353e..9780ac9768 100644
+--- a/doc/board/st/stm32mp1.rst
++++ b/doc/board/st/stm32mp1.rst
+@@ -620,7 +620,7 @@ Prerequisite: check if a MAC address isn't yet programmed in OTP
+     STM32MP> env print ethaddr
+     ## Error: "ethaddr" not defined
+ 
+-3) check lock status of fuse 57 & 58 (at 0x39, 0=unlocked, 1=locked)::
++3) check lock status of fuse 57 & 58 (at 0x39, 0=unlocked, 0x40000000=locked)::
+ 
+     STM32MP> fuse sense 0 0x10000039 2
+     Sensing bank 0:
+@@ -640,11 +640,11 @@ Example to set mac address "12:34:56:78:9a:bc"
+ 
+ 3) Lock OTP::
+ 
+-    STM32MP> fuse prog 0 0x10000039 1 1
++    STM32MP> fuse prog 0 0x10000039 0x40000000 0x40000000
+ 
+     STM32MP> fuse sense 0 0x10000039 2
+     Sensing bank 0:
+-       Word 0x10000039: 00000001 00000001
++       Word 0x10000039: 40000000 40000000
+ 
+ 4) next REBOOT, in the trace::
+ 
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0092-tee-optee-fix-uuid-comparisons-on-service-discovery.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0092-tee-optee-fix-uuid-comparisons-on-service-discovery.patch
new file mode 100644
index 00000000..a1f48466
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0092-tee-optee-fix-uuid-comparisons-on-service-discovery.patch
@@ -0,0 +1,36 @@
+From 8f28ec404b44e551b2c27d0f26dfd55276507e16 Mon Sep 17 00:00:00 2001
+From: Ilias Apalodimas <ilias.apalodimas@linaro.org>
+Date: Thu, 19 Jan 2023 11:21:37 +0200
+Subject: [PATCH 092/117] tee: optee: fix uuid comparisons on service discovery
+
+When comparing UUIDs for discovered services we only compare up to the
+ptr size instead of the entire UUID
+
+[Backport of commit eda976d36a37 ("tee: optee: fix uuid comparisons on
+ service discovery")]
+
+Fixes: 94ccfb78a4d61 ("drivers: tee: optee: discover OP-TEE services")
+Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
+Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
+Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
+Change-Id: I13167d5cbd0f13a771499e0468a00a1873e0ed5c
+---
+ drivers/tee/optee/core.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c
+index 88e23d252b..9a9b697e91 100644
+--- a/drivers/tee/optee/core.c
++++ b/drivers/tee/optee/core.c
+@@ -73,7 +73,7 @@ static struct optee_service *find_service_driver(const struct tee_optee_ta_uuid
+ 
+ 	for (idx = 0; idx < service_cnt; idx++, service++) {
+ 		tee_optee_ta_uuid_to_octets(loc_uuid, &service->uuid);
+-		if (!memcmp(uuid, loc_uuid, sizeof(uuid)))
++		if (!memcmp(uuid, loc_uuid, sizeof(*uuid)))
+ 			return service;
+ 	}
+ 
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0095-cmd-clk-probe-the-clock-before-dump-them.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0095-cmd-clk-probe-the-clock-before-dump-them.patch
new file mode 100644
index 00000000..3893be5b
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0095-cmd-clk-probe-the-clock-before-dump-them.patch
@@ -0,0 +1,80 @@
+From 3b6d6fdc7e5decb52f533c7049938ba1dd8d278d Mon Sep 17 00:00:00 2001
+From: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Date: Tue, 13 Dec 2022 14:57:10 +0100
+Subject: [PATCH 095/117] cmd: clk: probe the clock before dump them
+
+The clock UCLASS need to be probed to allow availability of the
+private data (struct clk *), get in show_clks() with dev_get_clk_ptr()
+before use them.
+
+Without this patch the clock dump can cause crash because all the
+private data are not available before calling the API clk_get_rate().
+
+It is the case for the SCMI clocks, priv->channel is needed for
+scmi_clk_get_rate() and it is initialized only in scmi_clk_probe().
+This issue causes a crash for "clk dump" command on STM32MP135F-DK board
+for SCMI clock not yet probed.
+
+[Backport of commit c40251c120fa ("cmd: clk: probe the clock before dump
+ them")]
+
+Fixes: 1a725e229096 ("clk: fix clock tree dump to properly dump out every registered clock")
+Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Reviewed-by: Sean Anderson <seanga2@gmail.com>
+Link: https://lore.kernel.org/r/20221213145708.v2.1.Ia0bc6b272f1e2e3f37873c61d79138c2663c4055@changeid
+Change-Id: I1a9c695a185950bbbc9436856aeac65ea5e7b1fc
+Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/292111
+ACI: CIBUILD <MDG-smet-aci-builds@list.st.com>
+---
+ cmd/clk.c | 15 +++++----------
+ 1 file changed, 5 insertions(+), 10 deletions(-)
+
+diff --git a/cmd/clk.c b/cmd/clk.c
+index a483fd8981..ff7c7649a1 100644
+--- a/cmd/clk.c
++++ b/cmd/clk.c
+@@ -22,7 +22,7 @@ static void show_clks(struct udevice *dev, int depth, int last_flag)
+ 	u32 rate;
+ 
+ 	clkp = dev_get_clk_ptr(dev);
+-	if (device_get_uclass_id(dev) == UCLASS_CLK && clkp) {
++	if (clkp) {
+ 		parent = clk_get_parent(clkp);
+ 		if (!IS_ERR(parent) && depth == -1)
+ 			return;
+@@ -49,10 +49,11 @@ static void show_clks(struct udevice *dev, int depth, int last_flag)
+ 		printf("%s\n", dev->name);
+ 	}
+ 
+-	list_for_each_entry(child, &dev->child_head, sibling_node) {
++	device_foreach_child_probe(child, dev) {
++		if (device_get_uclass_id(child) != UCLASS_CLK)
++			continue;
+ 		if (child == dev)
+ 			continue;
+-
+ 		is_last = list_is_last(&child->sibling_node, &dev->child_head);
+ 		show_clks(child, depth, (last_flag << 1) | is_last);
+ 	}
+@@ -61,17 +62,11 @@ static void show_clks(struct udevice *dev, int depth, int last_flag)
+ int __weak soc_clk_dump(void)
+ {
+ 	struct udevice *dev;
+-	struct uclass *uc;
+-	int ret;
+-
+-	ret = uclass_get(UCLASS_CLK, &uc);
+-	if (ret)
+-		return ret;
+ 
+ 	printf(" Rate               Usecnt      Name\n");
+ 	printf("------------------------------------------\n");
+ 
+-	uclass_foreach_dev(dev, uc)
++	uclass_foreach_dev_probe(UCLASS_CLK, dev)
+ 		show_clks(dev, -1, 0);
+ 
+ 	return 0;
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0107-ARM-dts-stm32-fix-node-name-order-and-node-name-and-.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0107-ARM-dts-stm32-fix-node-name-order-and-node-name-and-.patch
new file mode 100644
index 00000000..6ffee461
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0107-ARM-dts-stm32-fix-node-name-order-and-node-name-and-.patch
@@ -0,0 +1,764 @@
+From 883cafe23509a6802d16cbdff2392a10058e7214 Mon Sep 17 00:00:00 2001
+From: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Date: Mon, 30 Jan 2023 14:52:46 +0100
+Subject: [PATCH 107/117] ARM: dts: stm32: fix node name order and node name
+ and node label typo issue
+
+    nodes name order has to be done according:
+     Subgroup"arm" by pseudo alphabetic order (as if nodes were all prefixed with "arm-"
+     cpus {} // like arm-cpu
+     cpuX_opp_table {}
+     intc {} //like arm-gic
+     arm-pmu {}
+     psci {} //like arm-psci
+     timer {} //like arm-timer
+    then subgroup "st specific" by alphabetic ordre
+     booster {}
+     clocks {}
+     pm-domain {}
+     thermal-zones {}
+
+    node name must following rules from https://elinux.org/Device_Tree_Linux
+        node names
+            should begin with a character in the range 'a' to 'z', 'A' to 'Z'
+            unit-address does not have a leading "0x" (the number is assumed to be hexadecimal)
+            unit-address does not have leading zeros
+            use dash "-" instead of underscore "_"
+
+            hex constants are lower case
+            use "0x" instead of "0X"
+            use a..f instead of A..F, eg 0xf instead of 0xF
+
+Fixes: 500327e2ea79 ("ARM: dts: stm32mp1: DT alignment with Linux kernel v5.8-rc1")
+Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/281307
+
+Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Signed-off-by: Aliaksei Karpovich <akarpovich@ilbers.de>
+Change-Id: I1401c299dec6aebd33c405f4adec3822fb586efc
+---
+ arch/arm/dts/stm32mp131.dtsi             |  48 +++----
+ arch/arm/dts/stm32mp15-pinctrl.dtsi      | 156 +++++++++++------------
+ arch/arm/dts/stm32mp15-scmi.dtsi         |   1 -
+ arch/arm/dts/stm32mp151.dtsi             |  50 ++++----
+ arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi |   2 +-
+ arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi |   2 +-
+ arch/arm/dts/stm32mp157c-ed1.dts         |  22 ++--
+ arch/arm/dts/stm32mp157c-ev1.dts         |   8 +-
+ arch/arm/dts/stm32mp15xx-dkx.dtsi        |  22 ++--
+ 9 files changed, 155 insertions(+), 156 deletions(-)
+
+diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi
+index 3cf51f09bc..89c61397db 100644
+--- a/arch/arm/dts/stm32mp131.dtsi
++++ b/arch/arm/dts/stm32mp131.dtsi
+@@ -22,6 +22,14 @@
+ 		};
+ 	};
+ 
++	intc: interrupt-controller@a0021000 {
++		compatible = "arm,cortex-a7-gic";
++		#interrupt-cells = <3>;
++		interrupt-controller;
++		reg = <0xa0021000 0x1000>,
++		      <0xa0022000 0x2000>;
++	};
++
+ 	arm-pmu {
+ 		compatible = "arm,cortex-a7-pmu";
+ 		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+@@ -29,6 +37,21 @@
+ 		interrupt-parent = <&intc>;
+ 	};
+ 
++	psci {
++		compatible = "arm,psci-1.0";
++		method = "smc";
++	};
++
++	timer {
++		compatible = "arm,armv7-timer";
++		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
++			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
++			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
++			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
++		interrupt-parent = <&intc>;
++		always-on;
++	};
++
+ 	firmware {
+ 		optee {
+ 			method = "smc";
+@@ -54,29 +77,6 @@
+ 		};
+ 	};
+ 
+-	intc: interrupt-controller@a0021000 {
+-		compatible = "arm,cortex-a7-gic";
+-		#interrupt-cells = <3>;
+-		interrupt-controller;
+-		reg = <0xa0021000 0x1000>,
+-		      <0xa0022000 0x2000>;
+-	};
+-
+-	psci {
+-		compatible = "arm,psci-1.0";
+-		method = "smc";
+-	};
+-
+-	timer {
+-		compatible = "arm,armv7-timer";
+-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+-			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+-			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+-			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+-		interrupt-parent = <&intc>;
+-		always-on;
+-	};
+-
+ 	soc {
+ 		compatible = "simple-bus";
+ 		#address-cells = <1>;
+@@ -244,7 +244,7 @@
+ 			#address-cells = <1>;
+ 			#size-cells = <1>;
+ 
+-			part_number_otp: part_number_otp@4 {
++			part_number_otp: part-number-otp@4 {
+ 				reg = <0x4 0x2>;
+ 			};
+ 			ts_cal1: calib@5c {
+diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi
+index 2cc9341d43..d2552ed2ea 100644
+--- a/arch/arm/dts/stm32mp15-pinctrl.dtsi
++++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi
+@@ -188,7 +188,7 @@
+ 		};
+ 	};
+ 
+-	ethernet0_rgmii_pins_a: rgmii-0 {
++	ethernet0_rgmii_pins_a: ethernet0-rgmii-0 {
+ 		pins1 {
+ 			pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
+ 				 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
+@@ -219,7 +219,7 @@
+ 		};
+ 	};
+ 
+-	ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 {
++	ethernet0_rgmii_sleep_pins_a: ethernet0-rgmii-sleep-0 {
+ 		pins1 {
+ 			pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
+ 				 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
+@@ -239,7 +239,7 @@
+ 		};
+ 	};
+ 
+-	ethernet0_rgmii_pins_b: rgmii-1 {
++	ethernet0_rgmii_pins_b: ethernet0-rgmii-1 {
+ 		pins1 {
+ 			pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
+ 				 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
+@@ -270,7 +270,7 @@
+ 		};
+ 	};
+ 
+-	ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 {
++	ethernet0_rgmii_sleep_pins_b: ethernet0-rgmii-sleep-1 {
+ 		pins1 {
+ 			pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
+ 				 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
+@@ -290,7 +290,7 @@
+ 		 };
+ 	};
+ 
+-	ethernet0_rgmii_pins_c: rgmii-2 {
++	ethernet0_rgmii_pins_c: ethernet0-rgmii-2 {
+ 		pins1 {
+ 			pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
+ 				 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
+@@ -321,7 +321,7 @@
+ 		};
+ 	};
+ 
+-	ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 {
++	ethernet0_rgmii_sleep_pins_c: ethernet0-rgmii-sleep-2 {
+ 		pins1 {
+ 			pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
+ 				 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
+@@ -341,7 +341,7 @@
+ 		};
+ 	};
+ 
+-	ethernet0_rmii_pins_a: rmii-0 {
++	ethernet0_rmii_pins_a: ethernet0-rmii-0 {
+ 		pins1 {
+ 			pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
+ 				 <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
+@@ -361,7 +361,7 @@
+ 		};
+ 	};
+ 
+-	ethernet0_rmii_sleep_pins_a: rmii-sleep-0 {
++	ethernet0_rmii_sleep_pins_a: ethernet0-rmii-sleep-0 {
+ 		pins1 {
+ 			pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
+ 				 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
+@@ -375,7 +375,7 @@
+ 		};
+ 	};
+ 
+-	ethernet0_rmii_pins_b: rmii-1 {
++	ethernet0_rmii_pins_b: ethernet0-rmii-1 {
+ 		pins1 {
+ 			pinmux = <STM32_PINMUX('B', 5, AF0)>, /* ETH1_CLK */
+ 				<STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */
+@@ -402,7 +402,7 @@
+ 		};
+ 	};
+ 
+-	ethernet0_rmii_sleep_pins_b: rmii-sleep-1 {
++	ethernet0_rmii_sleep_pins_b: ethernet0-rmii-sleep-1 {
+ 		pins1 {
+ 			pinmux = <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
+ 				<STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_CRS_DV */
+@@ -416,7 +416,7 @@
+ 		};
+ 	};
+ 
+-	ethernet0_rmii_pins_c: rmii-2 {
++	ethernet0_rmii_pins_c: ethernet0-rmii-2 {
+ 		pins1 {
+ 			pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
+ 				 <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
+@@ -436,7 +436,7 @@
+ 		};
+ 	};
+ 
+-	ethernet0_rmii_sleep_pins_c: rmii-sleep-2 {
++	ethernet0_rmii_sleep_pins_c: ethernet0-rmii-sleep-2 {
+ 		pins1 {
+ 			pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
+ 				 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
+@@ -960,36 +960,6 @@
+ 		};
+ 	};
+ 
+-	mco1_pins_a: mco1-0 {
+-		pins {
+-			pinmux = <STM32_PINMUX('A', 13, AF2)>; /* MCO1 */
+-			bias-disable;
+-			drive-push-pull;
+-			slew-rate = <1>;
+-		};
+-	};
+-
+-	mco1_sleep_pins_a: mco1-sleep-0 {
+-		pins {
+-			pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* MCO1 */
+-		};
+-	};
+-
+-	mco2_pins_a: mco2-0 {
+-		pins {
+-			pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
+-			bias-disable;
+-			drive-push-pull;
+-			slew-rate = <2>;
+-		};
+-	};
+-
+-	mco2_sleep_pins_a: mco2-sleep-0 {
+-		pins {
+-			pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */
+-		};
+-	};
+-
+ 	m_can1_pins_a: m-can1-0 {
+ 		pins1 {
+ 			pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
+@@ -1003,7 +973,7 @@
+ 		};
+ 	};
+ 
+-	m_can1_sleep_pins_a: m_can1-sleep-0 {
++	m_can1_sleep_pins_a: m-can1-sleep-0 {
+ 		pins {
+ 			pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
+ 				 <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
+@@ -1023,7 +993,7 @@
+ 		};
+ 	};
+ 
+-	m_can1_sleep_pins_b: m_can1-sleep-1 {
++	m_can1_sleep_pins_b: m-can1-sleep-1 {
+ 		pins {
+ 			pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */
+ 				 <STM32_PINMUX('A', 11, ANALOG)>; /* CAN1_RX */
+@@ -1043,7 +1013,7 @@
+ 		};
+ 	};
+ 
+-	m_can1_sleep_pins_c: m_can1-sleep-2 {
++	m_can1_sleep_pins_c: m-can1-sleep-2 {
+ 		pins {
+ 			pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
+ 				 <STM32_PINMUX('H', 14, ANALOG)>; /* CAN1_RX */
+@@ -1063,13 +1033,43 @@
+ 		};
+ 	};
+ 
+-	m_can2_sleep_pins_a: m_can2-sleep-0 {
++	m_can2_sleep_pins_a: m-can2-sleep-0 {
+ 		pins {
+ 			pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* CAN2_TX */
+ 				 <STM32_PINMUX('B', 5, ANALOG)>; /* CAN2_RX */
+ 		};
+ 	};
+ 
++	mco1_pins_a: mco1-0 {
++		pins {
++			pinmux = <STM32_PINMUX('A', 13, AF2)>; /* MCO1 */
++			bias-disable;
++			drive-push-pull;
++			slew-rate = <1>;
++		};
++	};
++
++	mco1_sleep_pins_a: mco1-sleep-0 {
++		pins {
++			pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* MCO1 */
++		};
++	};
++
++	mco2_pins_a: mco2-0 {
++		pins {
++			pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
++			bias-disable;
++			drive-push-pull;
++			slew-rate = <2>;
++		};
++	};
++
++	mco2_sleep_pins_a: mco2-sleep-0 {
++		pins {
++			pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */
++		};
++	};
++
+ 	pwm1_pins_a: pwm1-0 {
+ 		pins {
+ 			pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */
+@@ -1245,21 +1245,6 @@
+ 		};
+ 	};
+ 
+-	qspi_clk_pins_a: qspi-clk-0 {
+-		pins {
+-			pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
+-			bias-disable;
+-			drive-push-pull;
+-			slew-rate = <3>;
+-		};
+-	};
+-
+-	qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
+-		pins {
+-			pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
+-		};
+-	};
+-
+ 	qspi_bk1_pins_a: qspi-bk1-0 {
+ 		pins1 {
+ 			pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
+@@ -1316,6 +1301,21 @@
+ 		};
+ 	};
+ 
++	qspi_clk_pins_a: qspi-clk-0 {
++		pins {
++			pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
++			bias-disable;
++			drive-push-pull;
++			slew-rate = <3>;
++		};
++	};
++
++	qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
++		pins {
++			pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
++		};
++	};
++
+ 	sai2a_pins_a: sai2a-0 {
+ 		pins {
+ 			pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
+@@ -1459,6 +1459,18 @@
+ 		};
+ 	};
+ 
++	sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 {
++		pins1 {
++			pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
++				 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
++				 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
++				 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
++			slew-rate = <1>;
++			drive-push-pull;
++			bias-disable;
++		};
++	};
++
+ 	sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
+ 		pins1 {
+ 			pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+@@ -1483,18 +1495,6 @@
+ 		};
+ 	};
+ 
+-	sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 {
+-		pins1 {
+-			pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+-				 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+-				 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+-				 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
+-			slew-rate = <1>;
+-			drive-push-pull;
+-			bias-disable;
+-		};
+-	};
+-
+ 	sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
+ 		pins {
+ 			pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
+@@ -2354,16 +2354,16 @@
+ 		};
+ 	};
+ 
+-	usbotg_hs_pins_a: usbotg-hs-0 {
++	usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
+ 		pins {
+-			pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
++			pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
++				 <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */
+ 		};
+ 	};
+ 
+-	usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
++	usbotg_hs_pins_a: usbotg-hs-0 {
+ 		pins {
+-			pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
+-				 <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */
++			pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
+ 		};
+ 	};
+ };
+diff --git a/arch/arm/dts/stm32mp15-scmi.dtsi b/arch/arm/dts/stm32mp15-scmi.dtsi
+index 543f24c2f4..45335791cb 100644
+--- a/arch/arm/dts/stm32mp15-scmi.dtsi
++++ b/arch/arm/dts/stm32mp15-scmi.dtsi
+@@ -97,7 +97,6 @@
+ 	vdda1v1-supply = <&scmi_reg11>;
+ 	vdda1v8-supply = <&scmi_reg18>;
+ };
+-
+ /delete-node/ &clk_hse;
+ /delete-node/ &clk_hsi;
+ /delete-node/ &clk_lse;
+diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
+index 5d178b5d3c..029adaf9da 100644
+--- a/arch/arm/dts/stm32mp151.dtsi
++++ b/arch/arm/dts/stm32mp151.dtsi
+@@ -41,6 +41,14 @@
+ 		};
+ 	};
+ 
++	intc: interrupt-controller@a0021000 {
++		compatible = "arm,cortex-a7-gic";
++		#interrupt-cells = <3>;
++		interrupt-controller;
++		reg = <0xa0021000 0x1000>,
++		      <0xa0022000 0x2000>;
++	};
++
+ 	arm-pmu {
+ 		compatible = "arm,cortex-a7-pmu";
+ 		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+@@ -53,14 +61,6 @@
+ 		method = "smc";
+ 	};
+ 
+-	intc: interrupt-controller@a0021000 {
+-		compatible = "arm,cortex-a7-gic";
+-		#interrupt-cells = <3>;
+-		interrupt-controller;
+-		reg = <0xa0021000 0x1000>,
+-		      <0xa0022000 0x2000>;
+-	};
+-
+ 	timer {
+ 		compatible = "arm,armv7-timer";
+ 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+@@ -71,6 +71,12 @@
+ 	};
+ 
+ 	clocks {
++		clk_csi: clk-csi {
++			#clock-cells = <0>;
++			compatible = "fixed-clock";
++			clock-frequency = <4000000>;
++		};
++
+ 		clk_hse: clk-hse {
+ 			#clock-cells = <0>;
+ 			compatible = "fixed-clock";
+@@ -94,12 +100,12 @@
+ 			compatible = "fixed-clock";
+ 			clock-frequency = <32000>;
+ 		};
++	};
+ 
+-		clk_csi: clk-csi {
+-			#clock-cells = <0>;
+-			compatible = "fixed-clock";
+-			clock-frequency = <4000000>;
+-		};
++	booster: regulator-booster {
++		compatible = "st,stm32mp1-booster";
++		st,syscfg = <&syscfg>;
++		status = "disabled";
+ 	};
+ 
+ 	thermal-zones {
+@@ -127,12 +133,6 @@
+ 		};
+ 	};
+ 
+-	booster: regulator-booster {
+-		compatible = "st,stm32mp1-booster";
+-		st,syscfg = <&syscfg>;
+-		status = "disabled";
+-	};
+-
+ 	soc {
+ 		compatible = "simple-bus";
+ 		#address-cells = <1>;
+@@ -1230,7 +1230,7 @@
+ 			};
+ 		};
+ 
+-		pwr_mcu: pwr_mcu@50001014 {
++		pwr_mcu: pwr-mcu@50001014 {
+ 			compatible = "st,stm32mp151-pwr-mcu", "syscon";
+ 			reg = <0x50001014 0x4>;
+ 		};
+@@ -1389,7 +1389,7 @@
+ 			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&rcc HASH1>;
+ 			resets = <&rcc HASH1_R>;
+-			dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
++			dmas = <&mdma1 31 0x2 0x1000a02 0x0 0x0>;
+ 			dma-names = "in";
+ 			dma-maxburst = <2>;
+ 			status = "disabled";
+@@ -1650,7 +1650,7 @@
+ 			reg = <0x5c005000 0x400>;
+ 			#address-cells = <1>;
+ 			#size-cells = <1>;
+-			part_number_otp: part_number_otp@4 {
++			part_number_otp: part-number-otp@4 {
+ 				reg = <0x4 0x1>;
+ 			};
+ 			ts_cal1: calib@5c {
+@@ -1855,11 +1855,11 @@
+ 			      <0x30000000 0x40000>,
+ 			      <0x38000000 0x10000>;
+ 			resets = <&rcc MCU_R>;
+-			st,syscfg-holdboot = <&rcc 0x10C 0x1>;
++			st,syscfg-holdboot = <&rcc 0x10c 0x1>;
+ 			st,syscfg-tz = <&rcc 0x000 0x1>;
+ 			st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
+-			st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
+-			st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
++			st,syscfg-rsc-tbl = <&tamp 0x144 0xffffffff>;
++			st,syscfg-m4-state = <&tamp 0x148 0xffffffff>;
+ 			status = "disabled";
+ 		};
+ 	};
+diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
+index 1106295192..49be22378c 100644
+--- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
++++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
+@@ -48,7 +48,7 @@
+ #endif
+ 
+ 	led {
+-		red {
++		led-red {
+ 			label = "error";
+ 			gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+ 			default-state = "off";
+diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
+index cea661bce6..a1457916d2 100644
+--- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
++++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
+@@ -44,7 +44,7 @@
+ #endif
+ 
+ 	led {
+-		red {
++		led-red {
+ 			label = "error";
+ 			gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+ 			default-state = "off";
+diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
+index fe5c8f25ce..4ea8b69339 100644
+--- a/arch/arm/dts/stm32mp157c-ed1.dts
++++ b/arch/arm/dts/stm32mp157c-ed1.dts
+@@ -16,13 +16,17 @@
+ 	model = "STMicroelectronics STM32MP157C eval daughter";
+ 	compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
+ 
++	aliases {
++		serial0 = &uart4;
++	};
++
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
+ 	memory@c0000000 {
+ 		device_type = "memory";
+-		reg = <0xC0000000 0x40000000>;
++		reg = <0xc0000000 0x40000000>;
+ 	};
+ 
+ 	reserved-memory {
+@@ -72,11 +76,7 @@
+ 		};
+ 	};
+ 
+-	aliases {
+-		serial0 = &uart4;
+-	};
+-
+-	sd_switch: regulator-sd_switch {
++	sd_switch: regulator-sd-switch {
+ 		compatible = "regulator-gpio";
+ 		regulator-name = "sd_switch";
+ 		regulator-min-microvolt = <1800000>;
+@@ -272,7 +272,7 @@
+ 				interrupts = <IT_CURLIM_LDO6 0>;
+ 			};
+ 
+-			vref_ddr: vref_ddr {
++			vref_ddr: vref-ddr {
+ 				regulator-name = "vref_ddr";
+ 				regulator-always-on;
+ 			};
+@@ -282,16 +282,16 @@
+ 				interrupts = <IT_OCP_BOOST 0>;
+ 			};
+ 
+-			vbus_otg: pwr_sw1 {
++			vbus_otg: pwr-sw1 {
+ 				regulator-name = "vbus_otg";
+ 				interrupts = <IT_OCP_OTG 0>;
+-			 };
++			};
+ 
+-			 vbus_sw: pwr_sw2 {
++			vbus_sw: pwr-sw2 {
+ 				regulator-name = "vbus_sw";
+ 				interrupts = <IT_OCP_SWOUT 0>;
+ 				regulator-active-discharge = <1>;
+-			 };
++			};
+ 		};
+ 
+ 		onkey {
+diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts
+index 2d5db41ed6..97260da29b 100644
+--- a/arch/arm/dts/stm32mp157c-ev1.dts
++++ b/arch/arm/dts/stm32mp157c-ev1.dts
+@@ -13,16 +13,16 @@
+ 	model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
+ 	compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
+ 
+-	chosen {
+-		stdout-path = "serial0:115200n8";
+-	};
+-
+ 	aliases {
+ 		serial0 = &uart4;
+ 		serial1 = &usart3;
+ 		ethernet0 = &ethernet0;
+ 	};
+ 
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
+ 	clocks {
+ 		clk_ext_camera: clk-ext-camera {
+ 			#clock-cells = <0>;
+diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi
+index 34af90195d..613e645e0d 100644
+--- a/arch/arm/dts/stm32mp15xx-dkx.dtsi
++++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi
+@@ -124,14 +124,6 @@
+ 	status = "okay";
+ };
+ 
+-&crc1 {
+-	status = "okay";
+-};
+-
+-&dts {
+-	status = "okay";
+-};
+-
+ &cpu0{
+ 	cpu-supply = <&vddcore>;
+ };
+@@ -140,6 +132,14 @@
+ 	cpu-supply = <&vddcore>;
+ };
+ 
++&crc1 {
++	status = "okay";
++};
++
++&dts {
++	status = "okay";
++};
++
+ &ethernet0 {
+ 	status = "okay";
+ 	pinctrl-0 = <&ethernet0_rgmii_pins_a>;
+@@ -385,7 +385,7 @@
+ 				interrupts = <IT_CURLIM_LDO6 0>;
+ 			};
+ 
+-			vref_ddr: vref_ddr {
++			vref_ddr: vref-ddr {
+ 				regulator-name = "vref_ddr";
+ 				regulator-always-on;
+ 			};
+@@ -395,12 +395,12 @@
+ 				interrupts = <IT_OCP_BOOST 0>;
+ 			};
+ 
+-			vbus_otg: pwr_sw1 {
++			vbus_otg: pwr-sw1 {
+ 				regulator-name = "vbus_otg";
+ 				interrupts = <IT_OCP_OTG 0>;
+ 			 };
+ 
+-			 vbus_sw: pwr_sw2 {
++			vbus_sw: pwr-sw2 {
+ 				regulator-name = "vbus_sw";
+ 				interrupts = <IT_OCP_SWOUT 0>;
+ 				regulator-active-discharge = <1>;
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0108-ARM-dts-stm32-reordering-nodes-in-stm32mp151.dtsi-fi.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0108-ARM-dts-stm32-reordering-nodes-in-stm32mp151.dtsi-fi.patch
new file mode 100644
index 00000000..d82e9e32
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0108-ARM-dts-stm32-reordering-nodes-in-stm32mp151.dtsi-fi.patch
@@ -0,0 +1,120 @@
+From feb9e69f9e90ca08379384f624b97539ba423eee Mon Sep 17 00:00:00 2001
+From: Olivier Moysan <olivier.moysan@foss.st.com>
+Date: Wed, 2 Nov 2022 15:10:32 +0100
+Subject: [PATCH 108/117] ARM: dts: stm32: reordering nodes in stm32mp151.dtsi
+ file
+
+- move nodeName 'i2sx: audio-controller@aaaaaaaa' above
+nodeName 'spix: spi@aaaaaaaa'
+(ascii sorting)
+
+Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
+Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/linux-stm32/+/278993
+Change-Id: Iecce8f8b7219e76b1b10e424c82a89b90c8a221f
+Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/283881
+ACI: CITOOLS <MDG-smet-aci-reviews@list.st.com>
+ACI: CIBUILD <MDG-smet-aci-builds@list.st.com>
+Domain-Review: Arnaud POULIQUEN <arnaud.pouliquen@st.com>
+---
+ arch/arm/dts/stm32mp151.dtsi | 54 ++++++++++++++++++------------------
+ 1 file changed, 27 insertions(+), 27 deletions(-)
+
+diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
+index 029adaf9da..3fdd249b43 100644
+--- a/arch/arm/dts/stm32mp151.dtsi
++++ b/arch/arm/dts/stm32mp151.dtsi
+@@ -422,6 +422,17 @@
+ 			};
+ 		};
+ 
++		i2s2: audio-controller@4000b000 {
++			compatible = "st,stm32h7-i2s";
++			#sound-dai-cells = <0>;
++			reg = <0x4000b000 0x400>;
++			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
++			dmas = <&dmamux1 39 0x400 0x01>,
++			       <&dmamux1 40 0x400 0x01>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++		};
++
+ 		spi2: spi@4000b000 {
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+@@ -436,13 +447,13 @@
+ 			status = "disabled";
+ 		};
+ 
+-		i2s2: audio-controller@4000b000 {
++		i2s3: audio-controller@4000c000 {
+ 			compatible = "st,stm32h7-i2s";
+ 			#sound-dai-cells = <0>;
+-			reg = <0x4000b000 0x400>;
+-			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+-			dmas = <&dmamux1 39 0x400 0x01>,
+-			       <&dmamux1 40 0x400 0x01>;
++			reg = <0x4000c000 0x400>;
++			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
++			dmas = <&dmamux1 61 0x400 0x01>,
++			       <&dmamux1 62 0x400 0x01>;
+ 			dma-names = "rx", "tx";
+ 			status = "disabled";
+ 		};
+@@ -461,17 +472,6 @@
+ 			status = "disabled";
+ 		};
+ 
+-		i2s3: audio-controller@4000c000 {
+-			compatible = "st,stm32h7-i2s";
+-			#sound-dai-cells = <0>;
+-			reg = <0x4000c000 0x400>;
+-			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+-			dmas = <&dmamux1 61 0x400 0x01>,
+-			       <&dmamux1 62 0x400 0x01>;
+-			dma-names = "rx", "tx";
+-			status = "disabled";
+-		};
+-
+ 		spdifrx: audio-controller@4000d000 {
+ 			compatible = "st,stm32h7-spdifrx";
+ 			#sound-dai-cells = <0>;
+@@ -748,6 +748,17 @@
+ 			status = "disabled";
+ 		};
+ 
++		i2s1: audio-controller@44004000 {
++			compatible = "st,stm32h7-i2s";
++			#sound-dai-cells = <0>;
++			reg = <0x44004000 0x400>;
++			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
++			dmas = <&dmamux1 37 0x400 0x01>,
++			       <&dmamux1 38 0x400 0x01>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++		};
++
+ 		spi1: spi@44004000 {
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+@@ -762,17 +773,6 @@
+ 			status = "disabled";
+ 		};
+ 
+-		i2s1: audio-controller@44004000 {
+-			compatible = "st,stm32h7-i2s";
+-			#sound-dai-cells = <0>;
+-			reg = <0x44004000 0x400>;
+-			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+-			dmas = <&dmamux1 37 0x400 0x01>,
+-			       <&dmamux1 38 0x400 0x01>;
+-			dma-names = "rx", "tx";
+-			status = "disabled";
+-		};
+-
+ 		spi4: spi@44005000 {
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0110-configs-Resync-with-savedefconfig.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0110-configs-Resync-with-savedefconfig.patch
new file mode 100644
index 00000000..426610fa
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0110-configs-Resync-with-savedefconfig.patch
@@ -0,0 +1,56 @@
+From 101102042aa32d0888e42df91d0ff4e76956cfda Mon Sep 17 00:00:00 2001
+From: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Date: Fri, 16 Sep 2022 15:22:33 +0200
+Subject: [PATCH 110/117] configs: Resync with savedefconfig
+
+Rsync all defconfig files using moveconfig.py
+
+Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Change-Id: I0122b298a7b49801e173e3ff161bbe951c466220
+Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/269546
+Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
+---
+ configs/stm32mp13_defconfig         | 1 -
+ configs/stm32mp15_defconfig         | 1 -
+ configs/stm32mp15_trusted_defconfig | 1 -
+ 3 files changed, 3 deletions(-)
+
+diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig
+index 6e156c7ede..fa7872ca69 100644
+--- a/configs/stm32mp13_defconfig
++++ b/configs/stm32mp13_defconfig
+@@ -66,7 +66,6 @@ CONFIG_DM_REGULATOR_GPIO=y
+ CONFIG_DM_REGULATOR_SCMI=y
+ CONFIG_RESET_SCMI=y
+ CONFIG_DM_RNG=y
+-CONFIG_RNG_OPTEE=y
+ CONFIG_DM_RTC=y
+ CONFIG_RTC_STM32=y
+ CONFIG_SERIAL_RX_BUFFER=y
+diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig
+index 00fd9ac491..4b305518b6 100644
+--- a/configs/stm32mp15_defconfig
++++ b/configs/stm32mp15_defconfig
+@@ -124,7 +124,6 @@ CONFIG_DM_REGULATOR_SCMI=y
+ CONFIG_REMOTEPROC_STM32_COPRO=y
+ CONFIG_RESET_SCMI=y
+ CONFIG_DM_RNG=y
+-CONFIG_RNG_OPTEE=y
+ CONFIG_RNG_STM32MP1=y
+ CONFIG_DM_RTC=y
+ CONFIG_RTC_STM32=y
+diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
+index e0bb2d2834..465b520da0 100644
+--- a/configs/stm32mp15_trusted_defconfig
++++ b/configs/stm32mp15_trusted_defconfig
+@@ -124,7 +124,6 @@ CONFIG_DM_REGULATOR_STPMIC1=y
+ CONFIG_REMOTEPROC_STM32_COPRO=y
+ CONFIG_RESET_SCMI=y
+ CONFIG_DM_RNG=y
+-CONFIG_RNG_OPTEE=y
+ CONFIG_RNG_STM32MP1=y
+ CONFIG_DM_RTC=y
+ CONFIG_RTC_STM32=y
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0111-ARM-dts-stm32-remove-stm32mp157-scmi.dtb-from-compil.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0111-ARM-dts-stm32-remove-stm32mp157-scmi.dtb-from-compil.patch
new file mode 100644
index 00000000..b73d8e87
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0111-ARM-dts-stm32-remove-stm32mp157-scmi.dtb-from-compil.patch
@@ -0,0 +1,126 @@
+From 7bd54f8b0489847285fff4d3168e70959b5f17dc Mon Sep 17 00:00:00 2001
+From: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Date: Fri, 7 Oct 2022 11:03:51 +0200
+Subject: [PATCH 111/117] ARM: dts: stm32: remove stm32mp157*-scmi.dtb from
+ compilation
+
+To ease STM32MP157 ST boards rebase, remove stm32mp157*-scmi.dtb from
+compilation.
+stm32mp157*-scmi.dts will be used (after being renamed into .dtsi) as
+include in stm32mp157*.dts.
+Due to inclusion in stm32mp157*.dts, there is a special case
+regarding stm32mp157c-ev1-scmi.dts(i). Indeed, stm32mp15-scmi.dtsi
+include must be also removed to avoid double inclusion (-ev1.dts
+includes ed1.dts which includes stm32mp15-scmi.dtsi).
+
+Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Signed-off-by: Aliaksei Karpovich <akarpovich@ilbers.de>
+Change-Id: Ia326c890f6182187cf7fd9a913546f95d85a53e1
+Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/270205
+---
+ arch/arm/dts/Makefile                                        | 4 ----
+ .../{stm32mp157a-dk1-scmi.dts => stm32mp157a-dk1-scmi.dtsi}  | 3 ---
+ .../{stm32mp157c-dk2-scmi.dts => stm32mp157c-dk2-scmi.dtsi}  | 3 ---
+ .../{stm32mp157c-ed1-scmi.dts => stm32mp157c-ed1-scmi.dtsi}  | 3 ---
+ .../{stm32mp157c-ev1-scmi.dts => stm32mp157c-ev1-scmi.dtsi}  | 5 -----
+ 5 files changed, 18 deletions(-)
+ rename arch/arm/dts/{stm32mp157a-dk1-scmi.dts => stm32mp157a-dk1-scmi.dtsi} (97%)
+ rename arch/arm/dts/{stm32mp157c-dk2-scmi.dts => stm32mp157c-dk2-scmi.dtsi} (97%)
+ rename arch/arm/dts/{stm32mp157c-ed1-scmi.dts => stm32mp157c-ed1-scmi.dtsi} (97%)
+ rename arch/arm/dts/{stm32mp157c-ev1-scmi.dts => stm32mp157c-ev1-scmi.dtsi} (95%)
+
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index 1b6c8467d7..4693fe13c1 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -1185,17 +1185,13 @@ dtb-$(CONFIG_STM32MP13x) += \
+ 
+ dtb-$(CONFIG_STM32MP15x) += \
+ 	stm32mp157a-dk1.dtb \
+-	stm32mp157a-dk1-scmi.dtb \
+ 	stm32mp157a-icore-stm32mp1-ctouch2.dtb \
+ 	stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
+ 	stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
+ 	stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
+ 	stm32mp157c-dk2.dtb \
+-	stm32mp157c-dk2-scmi.dtb \
+ 	stm32mp157c-ed1.dtb \
+-	stm32mp157c-ed1-scmi.dtb \
+ 	stm32mp157c-ev1.dtb \
+-	stm32mp157c-ev1-scmi.dtb \
+ 	stm32mp157c-odyssey.dtb \
+ 	stm32mp15xx-dhcom-drc02.dtb \
+ 	stm32mp15xx-dhcom-pdk2.dtb \
+diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/dts/stm32mp157a-dk1-scmi.dtsi
+similarity index 97%
+rename from arch/arm/dts/stm32mp157a-dk1-scmi.dts
+rename to arch/arm/dts/stm32mp157a-dk1-scmi.dtsi
+index e539cc80be..ea8daa1053 100644
+--- a/arch/arm/dts/stm32mp157a-dk1-scmi.dts
++++ b/arch/arm/dts/stm32mp157a-dk1-scmi.dtsi
+@@ -4,9 +4,6 @@
+  * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+  */
+ 
+-/dts-v1/;
+-
+-#include "stm32mp157a-dk1.dts"
+ #include "stm32mp15-scmi.dtsi"
+ 
+ / {
+diff --git a/arch/arm/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/dts/stm32mp157c-dk2-scmi.dtsi
+similarity index 97%
+rename from arch/arm/dts/stm32mp157c-dk2-scmi.dts
+rename to arch/arm/dts/stm32mp157c-dk2-scmi.dtsi
+index 97e4f94b0a..84a27ad0d0 100644
+--- a/arch/arm/dts/stm32mp157c-dk2-scmi.dts
++++ b/arch/arm/dts/stm32mp157c-dk2-scmi.dtsi
+@@ -4,9 +4,6 @@
+  * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+  */
+ 
+-/dts-v1/;
+-
+-#include "stm32mp157c-dk2.dts"
+ #include "stm32mp15-scmi.dtsi"
+ 
+ / {
+diff --git a/arch/arm/dts/stm32mp157c-ed1-scmi.dts b/arch/arm/dts/stm32mp157c-ed1-scmi.dtsi
+similarity index 97%
+rename from arch/arm/dts/stm32mp157c-ed1-scmi.dts
+rename to arch/arm/dts/stm32mp157c-ed1-scmi.dtsi
+index 9cf0a44d2f..e69fd28ab1 100644
+--- a/arch/arm/dts/stm32mp157c-ed1-scmi.dts
++++ b/arch/arm/dts/stm32mp157c-ed1-scmi.dtsi
+@@ -4,9 +4,6 @@
+  * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+  */
+ 
+-/dts-v1/;
+-
+-#include "stm32mp157c-ed1.dts"
+ #include "stm32mp15-scmi.dtsi"
+ 
+ / {
+diff --git a/arch/arm/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/dts/stm32mp157c-ev1-scmi.dtsi
+similarity index 95%
+rename from arch/arm/dts/stm32mp157c-ev1-scmi.dts
+rename to arch/arm/dts/stm32mp157c-ev1-scmi.dtsi
+index 3b9dd6f4cc..b96aa309dd 100644
+--- a/arch/arm/dts/stm32mp157c-ev1-scmi.dts
++++ b/arch/arm/dts/stm32mp157c-ev1-scmi.dtsi
+@@ -4,11 +4,6 @@
+  * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+  */
+ 
+-/dts-v1/;
+-
+-#include "stm32mp157c-ev1.dts"
+-#include "stm32mp15-scmi.dtsi"
+-
+ / {
+ 	model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother";
+ 	compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1",
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0112-ARM-dts-stm32-include-board-scmi.dtsi-in-each-board-.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0112-ARM-dts-stm32-include-board-scmi.dtsi-in-each-board-.patch
new file mode 100644
index 00000000..8c8228a4
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0112-ARM-dts-stm32-include-board-scmi.dtsi-in-each-board-.patch
@@ -0,0 +1,878 @@
+From ac826ce0ed6dc66c2e3087540b0d17e6b3c03444 Mon Sep 17 00:00:00 2001
+From: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Date: Fri, 7 Oct 2022 11:13:24 +0200
+Subject: [PATCH 112/117] ARM: dts: stm32: include <board>-scmi.dtsi in each
+ <board>.dts
+
+Now that double inclusion is avoided, <board>-scmi.dtsi include can be
+safely added in <board>.dts, to add SCMI support on STM32MP15 boards.
+
+As the STMicroelectronics board now support SCMI by default, this patch
+also move the U-Boot add-on files <board>-scmi-u-boot.dts to
+<board>-u-boot.dtsi and update the associated documentation.
+
+Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Signed-off-by: Aliaksei Karpovich <akarpovich@ilbers.de>
+Change-Id: I3675cbaef85beba02ff53292745d73f970addcbf
+Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/270206
+---
+ arch/arm/dts/stm32mp15-scmi-u-boot.dtsi       |  20 +-
+ arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi |  55 -----
+ arch/arm/dts/stm32mp157a-dk1-scmi.dtsi        |   3 -
+ arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi      | 162 +--------------
+ arch/arm/dts/stm32mp157a-dk1.dts              |   1 +
+ arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi |   6 -
+ arch/arm/dts/stm32mp157c-dk2-scmi.dtsi        |   3 -
+ arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi      |   4 +-
+ arch/arm/dts/stm32mp157c-dk2.dts              |   1 +
+ arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi |  45 -----
+ arch/arm/dts/stm32mp157c-ed1-scmi.dtsi        |   3 -
+ arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi      | 189 +-----------------
+ arch/arm/dts/stm32mp157c-ed1.dts              |   1 +
+ arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi |  17 --
+ arch/arm/dts/stm32mp157c-ev1-scmi.dtsi        |   4 -
+ arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi      |  40 +---
+ arch/arm/dts/stm32mp157c-ev1.dts              |   1 +
+ doc/board/st/stm32mp1.rst                     |  26 +--
+ 18 files changed, 37 insertions(+), 544 deletions(-)
+ delete mode 100644 arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
+ delete mode 100644 arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi
+ delete mode 100644 arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
+ delete mode 100644 arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi
+
+diff --git a/arch/arm/dts/stm32mp15-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp15-scmi-u-boot.dtsi
+index 314fc39a05..3f50eda62a 100644
+--- a/arch/arm/dts/stm32mp15-scmi-u-boot.dtsi
++++ b/arch/arm/dts/stm32mp15-scmi-u-boot.dtsi
+@@ -25,6 +25,17 @@
+ 		multiple-images;
+ 	};
+ 
++	firmware {
++		optee {
++			u-boot,dm-pre-reloc;
++		};
++	};
++
++	/* need PSCI for sysreset during board_f */
++	psci {
++		u-boot,dm-pre-proper;
++	};
++
+ 	soc {
+ 		u-boot,dm-pre-reloc;
+ 
+@@ -39,11 +50,6 @@
+ 			status = "okay";
+ 		};
+ 	};
+-
+-	/* need PSCI for sysreset during board_f */
+-	psci {
+-		u-boot,dm-pre-proper;
+-	};
+ };
+ 
+ &bsec {
+@@ -98,10 +104,6 @@
+ 	u-boot,dm-pre-reloc;
+ };
+ 
+-&optee {
+-	u-boot,dm-pre-proper;
+-};
+-
+ &iwdg2 {
+ 	u-boot,dm-pre-reloc;
+ };
+diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
+deleted file mode 100644
+index 92fdf09872..0000000000
+--- a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
++++ /dev/null
+@@ -1,55 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+-/*
+- * Copyright : STMicroelectronics 2022
+- */
+-
+-#include "stm32mp15-scmi-u-boot.dtsi"
+-
+-/ {
+-	aliases {
+-		i2c3 = &i2c4;
+-		usb0 = &usbotg_hs;
+-	};
+-
+-	config {
+-		u-boot,boot-led = "heartbeat";
+-		u-boot,error-led = "error";
+-		u-boot,mmc-env-partition = "u-boot-env";
+-		st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
+-		st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+-		st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+-	};
+-
+-	led {
+-		red {
+-			label = "error";
+-			gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+-			default-state = "off";
+-			status = "okay";
+-		};
+-	};
+-};
+-
+-&adc {
+-	status = "okay";
+-};
+-
+-&uart4 {
+-	u-boot,dm-pre-reloc;
+-};
+-
+-&uart4_pins_a {
+-	u-boot,dm-pre-reloc;
+-	pins1 {
+-		u-boot,dm-pre-reloc;
+-	};
+-	pins2 {
+-		u-boot,dm-pre-reloc;
+-		/* pull-up on rx to avoid floating level */
+-		bias-pull-up;
+-	};
+-};
+-
+-&usbotg_hs {
+-	u-boot,force-b-session-valid;
+-};
+diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi.dtsi b/arch/arm/dts/stm32mp157a-dk1-scmi.dtsi
+index ea8daa1053..673b736cc6 100644
+--- a/arch/arm/dts/stm32mp157a-dk1-scmi.dtsi
++++ b/arch/arm/dts/stm32mp157a-dk1-scmi.dtsi
+@@ -7,9 +7,6 @@
+ #include "stm32mp15-scmi.dtsi"
+ 
+ / {
+-	model = "STMicroelectronics STM32MP157A-DK1 SCMI Discovery Board";
+-	compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157a-dk1", "st,stm32mp157";
+-
+ 	reserved-memory {
+ 		optee@de000000 {
+ 			reg = <0xde000000 0x2000000>;
+diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
+index 49be22378c..8916cda1ad 100644
+--- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
++++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
+@@ -1,52 +1,25 @@
+-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
++// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+ /*
+- * Copyright : STMicroelectronics 2018
++ * Copyright : STMicroelectronics 2022
+  */
+ 
+-#include <dt-bindings/clock/stm32mp1-clksrc.h>
+-#include "stm32mp15-u-boot.dtsi"
+-#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
++#include "stm32mp15-scmi-u-boot.dtsi"
+ 
+ / {
+ 	aliases {
+ 		i2c3 = &i2c4;
+ 		usb0 = &usbotg_hs;
+ 	};
++
+ 	config {
+ 		u-boot,boot-led = "heartbeat";
+ 		u-boot,error-led = "error";
+-		u-boot,mmc-env-partition = "fip";
++		u-boot,mmc-env-partition = "u-boot-env";
+ 		st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
+ 		st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ 		st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ 	};
+ 
+-#if defined(CONFIG_STM32MP15x_STM32IMAGE) || defined(CONFIG_SPL)
+-	config {
+-		u-boot,mmc-env-partition = "ssbl";
+-	};
+-#endif
+-
+-#ifdef CONFIG_STM32MP15x_STM32IMAGE
+-	/* only needed for boot with TF-A, witout FIP support */
+-	firmware {
+-		optee {
+-			compatible = "linaro,optee-tz";
+-			method = "smc";
+-		};
+-	};
+-
+-	reserved-memory {
+-		u-boot,dm-spl;
+-
+-		optee@de000000 {
+-			reg = <0xde000000 0x02000000>;
+-			no-map;
+-			u-boot,dm-spl;
+-		};
+-	};
+-#endif
+-
+ 	led {
+ 		led-red {
+ 			label = "error";
+@@ -61,131 +34,6 @@
+ 	status = "okay";
+ };
+ 
+-&clk_hse {
+-	st,digbypass;
+-};
+-
+-&i2c4 {
+-	u-boot,dm-pre-reloc;
+-};
+-
+-&i2c4_pins_a {
+-	u-boot,dm-pre-reloc;
+-	pins {
+-		u-boot,dm-pre-reloc;
+-	};
+-};
+-
+-&pmic {
+-	u-boot,dm-pre-reloc;
+-};
+-
+-&rcc {
+-	st,clksrc = <
+-		CLK_MPU_PLL1P
+-		CLK_AXI_PLL2P
+-		CLK_MCU_PLL3P
+-		CLK_PLL12_HSE
+-		CLK_PLL3_HSE
+-		CLK_PLL4_HSE
+-		CLK_RTC_LSE
+-		CLK_MCO1_DISABLED
+-		CLK_MCO2_DISABLED
+-	>;
+-
+-	st,clkdiv = <
+-		1 /*MPU*/
+-		0 /*AXI*/
+-		0 /*MCU*/
+-		1 /*APB1*/
+-		1 /*APB2*/
+-		1 /*APB3*/
+-		1 /*APB4*/
+-		2 /*APB5*/
+-		23 /*RTC*/
+-		0 /*MCO1*/
+-		0 /*MCO2*/
+-	>;
+-
+-	st,pkcs = <
+-		CLK_CKPER_HSE
+-		CLK_FMC_ACLK
+-		CLK_QSPI_ACLK
+-		CLK_ETH_DISABLED
+-		CLK_SDMMC12_PLL4P
+-		CLK_DSI_DSIPLL
+-		CLK_STGEN_HSE
+-		CLK_USBPHY_HSE
+-		CLK_SPI2S1_PLL3Q
+-		CLK_SPI2S23_PLL3Q
+-		CLK_SPI45_HSI
+-		CLK_SPI6_HSI
+-		CLK_I2C46_HSI
+-		CLK_SDMMC3_PLL4P
+-		CLK_USBO_USBPHY
+-		CLK_ADC_CKPER
+-		CLK_CEC_LSE
+-		CLK_I2C12_HSI
+-		CLK_I2C35_HSI
+-		CLK_UART1_HSI
+-		CLK_UART24_HSI
+-		CLK_UART35_HSI
+-		CLK_UART6_HSI
+-		CLK_UART78_HSI
+-		CLK_SPDIF_PLL4P
+-		CLK_FDCAN_PLL4R
+-		CLK_SAI1_PLL3Q
+-		CLK_SAI2_PLL3Q
+-		CLK_SAI3_PLL3Q
+-		CLK_SAI4_PLL3Q
+-		CLK_RNG1_LSI
+-		CLK_RNG2_LSI
+-		CLK_LPTIM1_PCLK1
+-		CLK_LPTIM23_PCLK3
+-		CLK_LPTIM45_LSE
+-	>;
+-
+-	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
+-	pll2: st,pll@1 {
+-		compatible = "st,stm32mp1-pll";
+-		reg = <1>;
+-		cfg = < 2 65 1 0 0 PQR(1,1,1) >;
+-		frac = < 0x1400 >;
+-		u-boot,dm-pre-reloc;
+-	};
+-
+-	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
+-	pll3: st,pll@2 {
+-		compatible = "st,stm32mp1-pll";
+-		reg = <2>;
+-		cfg = < 1 33 1 16 36 PQR(1,1,1) >;
+-		frac = < 0x1a04 >;
+-		u-boot,dm-pre-reloc;
+-	};
+-
+-	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
+-	pll4: st,pll@3 {
+-		compatible = "st,stm32mp1-pll";
+-		reg = <3>;
+-		cfg = < 3 98 5 7 7 PQR(1,1,1) >;
+-		u-boot,dm-pre-reloc;
+-	};
+-};
+-
+-&sdmmc1 {
+-	u-boot,dm-spl;
+-};
+-
+-&sdmmc1_b4_pins_a {
+-	u-boot,dm-spl;
+-	pins1 {
+-		u-boot,dm-spl;
+-	};
+-	pins2 {
+-		u-boot,dm-spl;
+-	};
+-};
+-
+ &uart4 {
+ 	u-boot,dm-pre-reloc;
+ };
+diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts
+index 4c8be9c8eb..59c37383f3 100644
+--- a/arch/arm/dts/stm32mp157a-dk1.dts
++++ b/arch/arm/dts/stm32mp157a-dk1.dts
+@@ -10,6 +10,7 @@
+ #include "stm32mp15-pinctrl.dtsi"
+ #include "stm32mp15xxac-pinctrl.dtsi"
+ #include "stm32mp15xx-dkx.dtsi"
++#include "stm32mp157a-dk1-scmi.dtsi"
+ 
+ / {
+ 	model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
+diff --git a/arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi
+deleted file mode 100644
+index 5a8fc15ab2..0000000000
+--- a/arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi
++++ /dev/null
+@@ -1,6 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+-/*
+- * Copyright : STMicroelectronics 2022
+- */
+-
+-#include "stm32mp157a-dk1-scmi-u-boot.dtsi"
+diff --git a/arch/arm/dts/stm32mp157c-dk2-scmi.dtsi b/arch/arm/dts/stm32mp157c-dk2-scmi.dtsi
+index 84a27ad0d0..6069c50671 100644
+--- a/arch/arm/dts/stm32mp157c-dk2-scmi.dtsi
++++ b/arch/arm/dts/stm32mp157c-dk2-scmi.dtsi
+@@ -7,9 +7,6 @@
+ #include "stm32mp15-scmi.dtsi"
+ 
+ / {
+-	model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board";
+-	compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157c-dk2", "st,stm32mp157";
+-
+ 	reserved-memory {
+ 		optee@de000000 {
+ 			reg = <0xde000000 0x2000000>;
+diff --git a/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi b/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi
+index 06ef3a4095..41f36278b6 100644
+--- a/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi
++++ b/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi
+@@ -1,6 +1,6 @@
+-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
++// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+ /*
+- * Copyright : STMicroelectronics 2018
++ * Copyright : STMicroelectronics 2022
+  */
+ 
+ #include "stm32mp157a-dk1-u-boot.dtsi"
+diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts
+index 2bc92ef3ae..496a801d49 100644
+--- a/arch/arm/dts/stm32mp157c-dk2.dts
++++ b/arch/arm/dts/stm32mp157c-dk2.dts
+@@ -11,6 +11,7 @@
+ #include "stm32mp15-pinctrl.dtsi"
+ #include "stm32mp15xxac-pinctrl.dtsi"
+ #include "stm32mp15xx-dkx.dtsi"
++#include "stm32mp157c-dk2-scmi.dtsi"
+ 
+ / {
+ 	model = "STMicroelectronics STM32MP157C-DK2 Discovery Board";
+diff --git a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
+deleted file mode 100644
+index 63948ef493..0000000000
+--- a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
++++ /dev/null
+@@ -1,45 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+-/*
+- * Copyright : STMicroelectronics 2022
+- */
+-
+-#include "stm32mp15-scmi-u-boot.dtsi"
+-
+-/ {
+-	aliases {
+-		i2c3 = &i2c4;
+-	};
+-
+-	config {
+-		u-boot,boot-led = "heartbeat";
+-		u-boot,error-led = "error";
+-		u-boot,mmc-env-partition = "u-boot-env";
+-		st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+-		st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+-	};
+-
+-	led {
+-		red {
+-			label = "error";
+-			gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+-			default-state = "off";
+-			status = "okay";
+-		};
+-	};
+-};
+-
+-&uart4 {
+-	u-boot,dm-pre-reloc;
+-};
+-
+-&uart4_pins_a {
+-	u-boot,dm-pre-reloc;
+-	pins1 {
+-		u-boot,dm-pre-reloc;
+-	};
+-	pins2 {
+-		u-boot,dm-pre-reloc;
+-		/* pull-up on rx to avoid floating level */
+-		bias-pull-up;
+-	};
+-};
+diff --git a/arch/arm/dts/stm32mp157c-ed1-scmi.dtsi b/arch/arm/dts/stm32mp157c-ed1-scmi.dtsi
+index e69fd28ab1..44c817bdf9 100644
+--- a/arch/arm/dts/stm32mp157c-ed1-scmi.dtsi
++++ b/arch/arm/dts/stm32mp157c-ed1-scmi.dtsi
+@@ -7,9 +7,6 @@
+ #include "stm32mp15-scmi.dtsi"
+ 
+ / {
+-	model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter";
+-	compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157";
+-
+ 	reserved-memory {
+ 		optee@fe000000 {
+ 			reg = <0xfe000000 0x2000000>;
+diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
+index a1457916d2..b181944354 100644
+--- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
++++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
+@@ -1,11 +1,9 @@
+-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
++// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+ /*
+- * Copyright : STMicroelectronics 2018
++ * Copyright : STMicroelectronics 2022
+  */
+ 
+-#include <dt-bindings/clock/stm32mp1-clksrc.h>
+-#include "stm32mp15-u-boot.dtsi"
+-#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
++#include "stm32mp15-scmi-u-boot.dtsi"
+ 
+ / {
+ 	aliases {
+@@ -15,34 +13,11 @@
+ 	config {
+ 		u-boot,boot-led = "heartbeat";
+ 		u-boot,error-led = "error";
+-		u-boot,mmc-env-partition = "fip";
++		u-boot,mmc-env-partition = "u-boot-env";
+ 		st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ 		st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ 	};
+ 
+-#if defined(CONFIG_STM32MP15x_STM32IMAGE) || defined(CONFIG_SPL)
+-	config {
+-		u-boot,mmc-env-partition = "ssbl";
+-	};
+-#endif
+-
+-#ifdef CONFIG_STM32MP15x_STM32IMAGE
+-	/* only needed for boot with TF-A, witout FIP support */
+-	firmware {
+-		optee {
+-			compatible = "linaro,optee-tz";
+-			method = "smc";
+-		};
+-	};
+-
+-	reserved-memory {
+-		optee@fe000000 {
+-			reg = <0xfe000000 0x02000000>;
+-			no-map;
+-		};
+-	};
+-#endif
+-
+ 	led {
+ 		led-red {
+ 			label = "error";
+@@ -53,162 +28,6 @@
+ 	};
+ };
+ 
+-&clk_hse {
+-	st,digbypass;
+-};
+-
+-&i2c4 {
+-	u-boot,dm-pre-reloc;
+-};
+-
+-&i2c4_pins_a {
+-	u-boot,dm-pre-reloc;
+-	pins {
+-		u-boot,dm-pre-reloc;
+-	};
+-};
+-
+-&pmic {
+-	u-boot,dm-pre-reloc;
+-};
+-
+-&rcc {
+-	st,clksrc = <
+-		CLK_MPU_PLL1P
+-		CLK_AXI_PLL2P
+-		CLK_MCU_PLL3P
+-		CLK_PLL12_HSE
+-		CLK_PLL3_HSE
+-		CLK_PLL4_HSE
+-		CLK_RTC_LSE
+-		CLK_MCO1_DISABLED
+-		CLK_MCO2_DISABLED
+-	>;
+-
+-	st,clkdiv = <
+-		1 /*MPU*/
+-		0 /*AXI*/
+-		0 /*MCU*/
+-		1 /*APB1*/
+-		1 /*APB2*/
+-		1 /*APB3*/
+-		1 /*APB4*/
+-		2 /*APB5*/
+-		23 /*RTC*/
+-		0 /*MCO1*/
+-		0 /*MCO2*/
+-	>;
+-
+-	st,pkcs = <
+-		CLK_CKPER_HSE
+-		CLK_FMC_ACLK
+-		CLK_QSPI_ACLK
+-		CLK_ETH_DISABLED
+-		CLK_SDMMC12_PLL4P
+-		CLK_DSI_DSIPLL
+-		CLK_STGEN_HSE
+-		CLK_USBPHY_HSE
+-		CLK_SPI2S1_PLL3Q
+-		CLK_SPI2S23_PLL3Q
+-		CLK_SPI45_HSI
+-		CLK_SPI6_HSI
+-		CLK_I2C46_HSI
+-		CLK_SDMMC3_PLL4P
+-		CLK_USBO_USBPHY
+-		CLK_ADC_CKPER
+-		CLK_CEC_LSE
+-		CLK_I2C12_HSI
+-		CLK_I2C35_HSI
+-		CLK_UART1_HSI
+-		CLK_UART24_HSI
+-		CLK_UART35_HSI
+-		CLK_UART6_HSI
+-		CLK_UART78_HSI
+-		CLK_SPDIF_PLL4P
+-		CLK_FDCAN_PLL4R
+-		CLK_SAI1_PLL3Q
+-		CLK_SAI2_PLL3Q
+-		CLK_SAI3_PLL3Q
+-		CLK_SAI4_PLL3Q
+-		CLK_RNG1_LSI
+-		CLK_RNG2_LSI
+-		CLK_LPTIM1_PCLK1
+-		CLK_LPTIM23_PCLK3
+-		CLK_LPTIM45_LSE
+-	>;
+-
+-	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
+-	pll2: st,pll@1 {
+-		compatible = "st,stm32mp1-pll";
+-		reg = <1>;
+-		cfg = < 2 65 1 0 0 PQR(1,1,1) >;
+-		frac = < 0x1400 >;
+-		u-boot,dm-pre-reloc;
+-	};
+-
+-	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
+-	pll3: st,pll@2 {
+-		compatible = "st,stm32mp1-pll";
+-		reg = <2>;
+-		cfg = < 1 33 1 16 36 PQR(1,1,1) >;
+-		frac = < 0x1a04 >;
+-		u-boot,dm-pre-reloc;
+-	};
+-
+-	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
+-	pll4: st,pll@3 {
+-		compatible = "st,stm32mp1-pll";
+-		reg = <3>;
+-		cfg = < 3 98 5 7 7 PQR(1,1,1) >;
+-		u-boot,dm-pre-reloc;
+-	};
+-};
+-
+-&sdmmc1 {
+-	u-boot,dm-spl;
+-};
+-
+-&sdmmc1_b4_pins_a {
+-	u-boot,dm-spl;
+-	pins1 {
+-		u-boot,dm-spl;
+-	};
+-	pins2 {
+-		u-boot,dm-spl;
+-	};
+-};
+-
+-&sdmmc1_dir_pins_a {
+-	u-boot,dm-spl;
+-	pins1 {
+-		u-boot,dm-spl;
+-	};
+-	pins2 {
+-		u-boot,dm-spl;
+-	};
+-};
+-
+-&sdmmc2 {
+-	u-boot,dm-spl;
+-};
+-
+-&sdmmc2_b4_pins_a {
+-	u-boot,dm-spl;
+-	pins1 {
+-		u-boot,dm-spl;
+-	};
+-	pins2 {
+-		u-boot,dm-spl;
+-	};
+-};
+-
+-&sdmmc2_d47_pins_a {
+-	u-boot,dm-spl;
+-	pins {
+-		u-boot,dm-spl;
+-	};
+-};
+-
+ &uart4 {
+ 	u-boot,dm-pre-reloc;
+ };
+diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
+index 4ea8b69339..dbb4077a03 100644
+--- a/arch/arm/dts/stm32mp157c-ed1.dts
++++ b/arch/arm/dts/stm32mp157c-ed1.dts
+@@ -9,6 +9,7 @@
+ #include "stm32mp15xc.dtsi"
+ #include "stm32mp15-pinctrl.dtsi"
+ #include "stm32mp15xxaa-pinctrl.dtsi"
++#include "stm32mp157c-ed1-scmi.dtsi"
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/mfd/st,stpmic1.h>
+ 
+diff --git a/arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi
+deleted file mode 100644
+index 71a94f9130..0000000000
+--- a/arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi
++++ /dev/null
+@@ -1,17 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+-/*
+- * Copyright : STMicroelectronics 2022
+- */
+-
+-#include "stm32mp157c-ed1-scmi-u-boot.dtsi"
+-
+-/ {
+-	aliases {
+-		gpio26 = &stmfx_pinctrl;
+-		i2c1 = &i2c2;
+-		i2c4 = &i2c5;
+-		pinctrl2 = &stmfx_pinctrl;
+-		spi0 = &qspi;
+-		usb0 = &usbotg_hs;
+-	};
+-};
+diff --git a/arch/arm/dts/stm32mp157c-ev1-scmi.dtsi b/arch/arm/dts/stm32mp157c-ev1-scmi.dtsi
+index b96aa309dd..6cd714b9f4 100644
+--- a/arch/arm/dts/stm32mp157c-ev1-scmi.dtsi
++++ b/arch/arm/dts/stm32mp157c-ev1-scmi.dtsi
+@@ -5,10 +5,6 @@
+  */
+ 
+ / {
+-	model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother";
+-	compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1",
+-		     "st,stm32mp157";
+-
+ 	reserved-memory {
+ 		optee@fe000000 {
+ 			reg = <0xfe000000 0x2000000>;
+diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
+index ec60486f41..29402b0f5a 100644
+--- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
++++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
+@@ -1,6 +1,6 @@
+-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
++// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+ /*
+- * Copyright : STMicroelectronics 2018
++ * Copyright : STMicroelectronics 2022
+  */
+ 
+ #include "stm32mp157c-ed1-u-boot.dtsi"
+@@ -15,39 +15,3 @@
+ 		usb0 = &usbotg_hs;
+ 	};
+ };
+-
+-&flash0 {
+-	u-boot,dm-spl;
+-};
+-
+-&qspi {
+-	u-boot,dm-spl;
+-};
+-
+-&qspi_clk_pins_a {
+-	u-boot,dm-spl;
+-	pins {
+-		u-boot,dm-spl;
+-	};
+-};
+-
+-&qspi_bk1_pins_a {
+-	u-boot,dm-spl;
+-	pins1 {
+-		u-boot,dm-spl;
+-	};
+-	pins2 {
+-		u-boot,dm-spl;
+-	};
+-};
+-
+-&qspi_bk2_pins_a {
+-	u-boot,dm-spl;
+-	pins1 {
+-		u-boot,dm-spl;
+-	};
+-	pins2 {
+-		u-boot,dm-spl;
+-	};
+-};
+-
+diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts
+index 97260da29b..e540baa504 100644
+--- a/arch/arm/dts/stm32mp157c-ev1.dts
++++ b/arch/arm/dts/stm32mp157c-ev1.dts
+@@ -6,6 +6,7 @@
+ /dts-v1/;
+ 
+ #include "stm32mp157c-ed1.dts"
++#include "stm32mp157c-ev1-scmi.dtsi"
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/input.h>
+ 
+diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst
+index c0b1daa041..7c695cfaf3 100644
+--- a/doc/board/st/stm32mp1.rst
++++ b/doc/board/st/stm32mp1.rst
+@@ -69,23 +69,21 @@ a Cortex-A frequency option:
+  - D : Cortex-A7 @ 800 MHz
+  - F : Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz
+ 
+-Currently the following boards are supported:
++Currently the following STMIcroelectronics boards are supported:
+ 
+  + stm32mp157a-dk1.dts
+  + stm32mp157c-dk2.dts
+  + stm32mp157c-ed1.dts
+  + stm32mp157c-ev1.dts
+- + stm32mp15xx-dhcor-avenger96.dts
+ 
+-The SCMI variant of each board is supported by a specific "scmi" device tree:
+- + stm32mp157a-dk1-scmi.dts
+- + stm32mp157c-dk2-scmi.dts
+- + stm32mp157c-ed1-scmi.dts
+- + stm32mp157c-ev1-scmi.dts
++These board with SCMI support are only managed with stm32mp15_defconfig,
++when the resources are secured with RCC_TZCR.TZEN=1 in OP-TEE. The access to
++these reset and clock resources are provided by OP-TEE and the associated SCMI
++services.
+ 
+-SCMI variant is used only with stm32mp15_defconfig, when the resources are
+-secured with RCC_TZCR.TZEN=1 in OP-TEE. The access to these reset and clock
+-resources are provided by OP-TEE and the associated SCMI services.
++Currently the following customer boards are supported:
++
++ + stm32mp15xx-dhcor-avenger96.dts
+ 
+ STM32MP13x
+ ``````````
+@@ -146,7 +144,7 @@ TF-A_ (BL2) initialize the DDR and loads the next stage binaries from a FIP file
+      the secure monitor to access to secure resources.
+    + HW_CONFIG: The hardware configuration file = the U-Boot device tree
+ 
+-The scmi variant of each device tree is only support with OP-TEE as secure
++The SCMI variant of each device tree is only support with OP-TEE as secure
+ monitor, with stm32mp15_defconfig.
+ 
+ The **Basic** boot chain with SPL (for STM32MP15x)
+@@ -261,12 +259,6 @@ Build Procedure
+ 
+   a) trusted boot with FIP on STM32MP15x ev1::
+ 
+-     # export KBUILD_OUTPUT=stm32mp15
+-     # make stm32mp15_defconfig
+-     # make DEVICE_TREE=stm32mp157c-ev1-scmi all
+-
+-    or without SCMI support
+-
+      # export KBUILD_OUTPUT=stm32mp15
+      # make stm32mp15_defconfig
+      # make DEVICE_TREE=stm32mp157c-ev1 all
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0113-ARM-dts-stm32-fullfill-diversity-with-OPP-for-STM32M.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0113-ARM-dts-stm32-fullfill-diversity-with-OPP-for-STM32M.patch
new file mode 100644
index 00000000..fc441652
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0113-ARM-dts-stm32-fullfill-diversity-with-OPP-for-STM32M.patch
@@ -0,0 +1,90 @@
+From 7a539c911deefe3706181c6ae2d0cf39cba2d649 Mon Sep 17 00:00:00 2001
+From: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Date: Fri, 7 Oct 2022 14:25:58 +0200
+Subject: [PATCH 113/117] ARM: dts: stm32: fullfill diversity with OPP for
+ STM32M15x SOCs
+
+This commit creates new files to manage security features and supported OPP
+on STM32MP15x SOCs. On STM32MP15xY, "Y" gives information:
+-Y = A means no cryp IP and no secure boot + A7-CPU@650MHz.
+-Y = C means cryp IP + optee + secure boot + A7-CPU@650MHz.
+-Y = D means no cryp IP and no secure boot + A7-CPU@800MHz.
+-Y = F means cryp IP + optee + secure boot + A7-CPU@800MHz.
+
+Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Change-Id: Iaf515146d37b983d08fa4969afd48f2d6e2606f3
+Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/270207
+---
+ arch/arm/dts/stm32mp15xa.dtsi |  5 +++++
+ arch/arm/dts/stm32mp15xc.dtsi |  2 ++
+ arch/arm/dts/stm32mp15xd.dtsi |  5 +++++
+ arch/arm/dts/stm32mp15xf.dtsi | 20 ++++++++++++++++++++
+ 4 files changed, 32 insertions(+)
+ create mode 100644 arch/arm/dts/stm32mp15xa.dtsi
+ create mode 100644 arch/arm/dts/stm32mp15xd.dtsi
+ create mode 100644 arch/arm/dts/stm32mp15xf.dtsi
+
+diff --git a/arch/arm/dts/stm32mp15xa.dtsi b/arch/arm/dts/stm32mp15xa.dtsi
+new file mode 100644
+index 0000000000..cc6456e71b
+--- /dev/null
++++ b/arch/arm/dts/stm32mp15xa.dtsi
+@@ -0,0 +1,5 @@
++// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
++/*
++ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
++ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
++ */
+diff --git a/arch/arm/dts/stm32mp15xc.dtsi b/arch/arm/dts/stm32mp15xc.dtsi
+index b06a55a2fa..f729b0d1bd 100644
+--- a/arch/arm/dts/stm32mp15xc.dtsi
++++ b/arch/arm/dts/stm32mp15xc.dtsi
+@@ -4,6 +4,8 @@
+  * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+  */
+ 
++#include "stm32mp15xa.dtsi"
++
+ / {
+ 	soc {
+ 		cryp1: cryp@54001000 {
+diff --git a/arch/arm/dts/stm32mp15xd.dtsi b/arch/arm/dts/stm32mp15xd.dtsi
+new file mode 100644
+index 0000000000..cc6456e71b
+--- /dev/null
++++ b/arch/arm/dts/stm32mp15xd.dtsi
+@@ -0,0 +1,5 @@
++// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
++/*
++ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
++ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
++ */
+diff --git a/arch/arm/dts/stm32mp15xf.dtsi b/arch/arm/dts/stm32mp15xf.dtsi
+new file mode 100644
+index 0000000000..ae4a14af6c
+--- /dev/null
++++ b/arch/arm/dts/stm32mp15xf.dtsi
+@@ -0,0 +1,20 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
++ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
++ */
++
++#include "stm32mp15xd.dtsi"
++
++/ {
++	soc {
++		cryp1: cryp@54001000 {
++			compatible = "st,stm32mp1-cryp";
++			reg = <0x54001000 0x400>;
++			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&rcc CRYP1>;
++			resets = <&rcc CRYP1_R>;
++			status = "disabled";
++		};
++	};
++};
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0114-ARM-dts-stm32-adapt-stm32mp157a-dk1-board-to-stm32-D.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0114-ARM-dts-stm32-adapt-stm32mp157a-dk1-board-to-stm32-D.patch
new file mode 100644
index 00000000..c36a3376
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0114-ARM-dts-stm32-adapt-stm32mp157a-dk1-board-to-stm32-D.patch
@@ -0,0 +1,32 @@
+From 1b571739597e723aab593d3b0678422a4a38a901 Mon Sep 17 00:00:00 2001
+From: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Date: Fri, 7 Oct 2022 14:27:02 +0200
+Subject: [PATCH 114/117] ARM: dts: stm32: adapt stm32mp157a-dk1 board to stm32
+ DT diversity
+
+To handle STM32MP15 SOCs diversity, some updates have to been done.
+This commit mainly adapts stm32mp157a-dk1 board to include the
+correct SOC version.
+
+Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Change-Id: If87b1308a90d445cf00764c2a907f4c029b5a1c9
+Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/270208
+---
+ arch/arm/dts/stm32mp157a-dk1.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts
+index 59c37383f3..8a8de1cbed 100644
+--- a/arch/arm/dts/stm32mp157a-dk1.dts
++++ b/arch/arm/dts/stm32mp157a-dk1.dts
+@@ -7,6 +7,7 @@
+ /dts-v1/;
+ 
+ #include "stm32mp157.dtsi"
++#include "stm32mp15xa.dtsi"
+ #include "stm32mp15-pinctrl.dtsi"
+ #include "stm32mp15xxac-pinctrl.dtsi"
+ #include "stm32mp15xx-dkx.dtsi"
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0117-ARM-dts-stm32-add-stm32mp157d-dk1-board-support.patch b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0117-ARM-dts-stm32-add-stm32mp157d-dk1-board-support.patch
new file mode 100644
index 00000000..49797447
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/files/stm32mp15x/0117-ARM-dts-stm32-add-stm32mp157d-dk1-board-support.patch
@@ -0,0 +1,103 @@
+From b4ba6aefe532646cd0035af7b4bffe40d6d31061 Mon Sep 17 00:00:00 2001
+From: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Date: Fri, 7 Oct 2022 14:39:33 +0200
+Subject: [PATCH 117/117] ARM: dts: stm32: add stm32mp157d-dk1 board support
+
+This commit adds stm32mp157d-dk1 board support. This board embeds a
+STM32MP157D SOC. This SOC contains the same level of feature than a
+STM32MP157A SOC but A7 clock frequency can reach 800MHz.
+
+Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Signed-off-by: Aliaksei Karpovich <akarpovich@ilbers.de>
+Change-Id: I1fd620847d2bbb9c3d8d461259f2cbd1a8aa6907
+Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/270210
+---
+ arch/arm/dts/Makefile                    |  1 +
+ arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi |  6 +++++
+ arch/arm/dts/stm32mp157d-dk1.dts         | 30 ++++++++++++++++++++++++
+ doc/board/st/stm32mp1.rst                |  2 ++
+ 4 files changed, 39 insertions(+)
+ create mode 100644 arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi
+ create mode 100644 arch/arm/dts/stm32mp157d-dk1.dts
+
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index f1e5f59b52..17fd978b07 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -1193,5 +1193,6 @@ dtb-$(CONFIG_STM32MP15x) += \
+ 	stm32mp157c-ed1.dtb \
+ 	stm32mp157c-ev1.dtb \
+ 	stm32mp157c-odyssey.dtb \
++	stm32mp157d-dk1.dtb \
+ 	stm32mp15xx-dhcom-drc02.dtb \
+ 	stm32mp15xx-dhcom-pdk2.dtb \
+diff --git a/arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi
+new file mode 100644
+index 0000000000..41f36278b6
+--- /dev/null
++++ b/arch/arm/dts/stm32mp157d-dk1-u-boot.dtsi
+@@ -0,0 +1,6 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
++/*
++ * Copyright : STMicroelectronics 2022
++ */
++
++#include "stm32mp157a-dk1-u-boot.dtsi"
+diff --git a/arch/arm/dts/stm32mp157d-dk1.dts b/arch/arm/dts/stm32mp157d-dk1.dts
+new file mode 100644
+index 0000000000..ad917a6e18
+--- /dev/null
++++ b/arch/arm/dts/stm32mp157d-dk1.dts
+@@ -0,0 +1,30 @@
++// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
++/*
++ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
++ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
++ */
++
++/dts-v1/;
++
++#include "stm32mp157.dtsi"
++#include "stm32mp15xd.dtsi"
++#include "stm32mp15-pinctrl.dtsi"
++#include "stm32mp15xxac-pinctrl.dtsi"
++#include "stm32mp15xx-dkx.dtsi"
++#include "stm32mp157a-dk1-scmi.dtsi"
++
++/ {
++	model = "STMicroelectronics STM32MP157D-DK1 Discovery Board";
++	compatible = "st,stm32mp157d-dk1", "st,stm32mp157";
++
++	aliases {
++		ethernet0 = &ethernet0;
++		serial0 = &uart4;
++		serial1 = &usart3;
++		serial2 = &uart7;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++};
+diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst
+index 85b35be9ca..11e15de821 100644
+--- a/doc/board/st/stm32mp1.rst
++++ b/doc/board/st/stm32mp1.rst
+@@ -75,5 +75,6 @@ Currently the following STMIcroelectronics boards are supported:
+  + stm32mp157c-dk2.dts
+  + stm32mp157c-ed1.dts
+  + stm32mp157c-ev1.dts
++ + stm32mp157d-dk1.dts
+ 
+ These board with SCMI support are only managed with stm32mp15_defconfig,
+@@ -191,6 +192,7 @@ The supported device trees for STM32MP15x (stm32mp15_trusted_defconfig and stm32
+ + dk1: Discovery board
+ 
+    + stm32mp157a-dk1
++   + stm32mp157d-dk1
+ 
+ + dk2: Discovery board = dk1 with a BT/WiFI combo and a DSI panel
+ 
+-- 
+2.39.2
+
diff --git a/meta-isar/recipes-bsp/u-boot/u-boot-stm32mp15x_2020.10.bb b/meta-isar/recipes-bsp/u-boot/u-boot-stm32mp15x_2020.10.bb
deleted file mode 100644
index fddeb52f..00000000
--- a/meta-isar/recipes-bsp/u-boot/u-boot-stm32mp15x_2020.10.bb
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright (c) Siemens AG, 2020
-#
-# SPDX-License-Identifier: MIT
-
-require u-boot-${PV}.inc
-
-SRC_URI += " \
-    file://0001-fdtdec-optionally-add-property-no-map-to-created-res.patch \
-    file://0002-optee-add-property-no-map-to-secure-reserved-memory.patch"
-
-COMPATIBLE_MACHINE = "stm32mp15x"
diff --git a/meta-isar/recipes-bsp/u-boot/u-boot-stm32mp15x_2022.10.bb b/meta-isar/recipes-bsp/u-boot/u-boot-stm32mp15x_2022.10.bb
new file mode 100644
index 00000000..09b55cee
--- /dev/null
+++ b/meta-isar/recipes-bsp/u-boot/u-boot-stm32mp15x_2022.10.bb
@@ -0,0 +1,47 @@
+#
+# Copyright (c) Siemens AG, 2020
+# Copyright (c) 2023-2025 ilbers GmbH
+#
+# SPDX-License-Identifier: MIT
+
+require recipes-bsp/u-boot/u-boot-custom.inc
+
+SRC_URI += " https://ftp.denx.de/pub/u-boot/u-boot-${PV}.tar.bz2 \
+    file://0003-drivers-tee-optee-remove-unused-probe-local-variable.patch \
+    file://0004-drivers-tee-optee-discover-OP-TEE-services.patch \
+    file://0005-drivers-rng-optee_rng-register-to-CONFIG_OPTEE_SERVI.patch \
+    file://0014-ARM-dts-stm32mp-alignment-with-v6.0-rc3.patch \
+    file://0016-board-st-stm32mp1-use-of-correct-compatible-string-t.patch \
+    file://0017-arm-stm32mp-add-defines-for-BSEC_LOCK-status-in-stm3.patch \
+    file://0022-ARM-dts-stm32mp15-update-DDR-node.patch \
+    file://0042-ARM-dts-stm32-update-SCMI-dedicated-file.patch \
+    file://0053-ARM-dts-stm32-add-sdmmc-cd-gpios-for-STM32MP135F-DK.patch \
+    file://0063-dm-pmic-ignore-disabled-node-in-pmic_bind_children.patch \
+    file://0069-tee-optee-don-t-fail-probe-because-of-optee-rng.patch \
+    file://0070-tee-optee-discover-services-dependent-on-tee-supplic.patch \
+    file://0071-optee-bind-the-TA-drivers-on-OP-TEE-node.patch \
+    file://0081-ARM-dts-stm32mp15-remove-clksrc-include-in-SCMI-dtsi.patch \
+    file://0083-ARM-dts-stm32-Add-timer-interrupts-on-stm32mp15.patch \
+    file://0084-stm32mp-cosmetic-Update-of-bsec-driver.patch \
+    file://0085-stm32mp-Add-OP-TEE-support-in-bsec-driver.patch \
+    file://0092-tee-optee-fix-uuid-comparisons-on-service-discovery.patch \
+    file://0095-cmd-clk-probe-the-clock-before-dump-them.patch \
+    file://0107-ARM-dts-stm32-fix-node-name-order-and-node-name-and-.patch \
+    file://0108-ARM-dts-stm32-reordering-nodes-in-stm32mp151.dtsi-fi.patch \
+    file://0110-configs-Resync-with-savedefconfig.patch \
+    file://0111-ARM-dts-stm32-remove-stm32mp157-scmi.dtb-from-compil.patch \
+    file://0112-ARM-dts-stm32-include-board-scmi.dtsi-in-each-board-.patch \
+    file://0113-ARM-dts-stm32-fullfill-diversity-with-OPP-for-STM32M.patch \
+    file://0114-ARM-dts-stm32-adapt-stm32mp157a-dk1-board-to-stm32-D.patch \
+    file://0117-ARM-dts-stm32-add-stm32mp157d-dk1-board-support.patch"
+
+SRC_URI[sha256sum] = "50b4482a505bc281ba8470c399a3c26e145e29b23500bc35c50debd7fa46bdf8"
+
+DEBIAN_BUILD_DEPENDS += ", swig, python3-setuptools, python3-dev:native, \
+    libssl-dev:native, libssl-dev:armhf"
+
+S = "${WORKDIR}/u-boot-${PV}"
+
+U_BOOT_EXTRA_BUILDARGS = "DEVICE_TREE=stm32mp157d-dk1"
+
+COMPATIBLE_MACHINE = "stm32mp15x"
diff --git a/meta-isar/recipes-kernel/linux/files/0001-ARM-dts-stm32-add-stm32mp157d-dk1-board-support.patch b/meta-isar/recipes-kernel/linux/files/0001-ARM-dts-stm32-add-stm32mp157d-dk1-board-support.patch
new file mode 100644
index 00000000..55fdde8c
--- /dev/null
+++ b/meta-isar/recipes-kernel/linux/files/0001-ARM-dts-stm32-add-stm32mp157d-dk1-board-support.patch
@@ -0,0 +1,60 @@
+diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile
+index 44b264c39..547cbb2ae 100644
+--- a/arch/arm/boot/dts/st/Makefile
++++ b/arch/arm/boot/dts/st/Makefile
+@@ -59,7 +59,8 @@ dtb-$(CONFIG_ARCH_STM32) += \
+ 	stm32mp157c-lxa-tac-gen1.dtb \
+ 	stm32mp157c-lxa-tac-gen2.dtb \
+ 	stm32mp157c-odyssey.dtb \
+-	stm32mp157c-phycore-stm32mp1-3.dtb
++	stm32mp157c-phycore-stm32mp1-3.dtb \
++	stm32mp157d-dk1.dtb
+ dtb-$(CONFIG_ARCH_U8500) += \
+ 	ste-snowball.dtb \
+ 	ste-hrefprev60-stuib.dtb \
+diff --git a/arch/arm/boot/dts/st/stm32mp157d-dk1.dts b/arch/arm/boot/dts/st/stm32mp157d-dk1.dts
+new file mode 100644
+index 000000000..5e5bc6df3
+--- /dev/null
++++ b/arch/arm/boot/dts/st/stm32mp157d-dk1.dts
+@@ -0,0 +1,29 @@
++// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
++/*
++ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
++ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
++ */
++
++/dts-v1/;
++
++#include "stm32mp157.dtsi"
++#include "stm32mp15xd.dtsi"
++#include "stm32mp15-pinctrl.dtsi"
++#include "stm32mp15xxac-pinctrl.dtsi"
++#include "stm32mp15xx-dkx.dtsi"
++
++/ {
++	model = "STMicroelectronics STM32MP157D-DK1 Discovery Board";
++	compatible = "st,stm32mp157d-dk1", "st,stm32mp157";
++
++	aliases {
++		ethernet0 = &ethernet0;
++		serial0 = &uart4;
++		serial1 = &usart3;
++		serial2 = &uart7;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++};
+diff --git a/arch/arm/boot/dts/st/stm32mp15xd.dtsi b/arch/arm/boot/dts/st/stm32mp15xd.dtsi
+new file mode 100644
+index 000000000..cc6456e71
+--- /dev/null
++++ b/arch/arm/boot/dts/st/stm32mp15xd.dtsi
+@@ -0,0 +1,5 @@
++// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
++/*
++ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
++ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
++ */
diff --git a/meta-isar/recipes-kernel/linux/linux-mainline_6.6.11.bb b/meta-isar/recipes-kernel/linux/linux-mainline_6.6.11.bb
index 2287e763..b44cbb78 100644
--- a/meta-isar/recipes-kernel/linux/linux-mainline_6.6.11.bb
+++ b/meta-isar/recipes-kernel/linux/linux-mainline_6.6.11.bb
@@ -14,7 +14,8 @@ SRC_URI += " \
     file://x86_64_defconfig \
     file://ftpm-module.cfg \
     file://subdir/no-ubifs-fs.cfg \
-    file://no-root-nfs.cfg;apply=no"
+    file://no-root-nfs.cfg;apply=no \
+    file://0001-ARM-dts-stm32-add-stm32mp157d-dk1-board-support.patch"
 
 SRC_URI[sha256sum] = "afe2e5a661bb886d762684ebea71607d1ee8cb9dd100279d2810ba20d9671e52"
 
diff --git a/meta-isar/scripts/lib/wic/canned-wks/stm32mp15x.wks.in b/meta-isar/scripts/lib/wic/canned-wks/stm32mp15x.wks.in
index 5d96f65f..ea2c558d 100644
--- a/meta-isar/scripts/lib/wic/canned-wks/stm32mp15x.wks.in
+++ b/meta-isar/scripts/lib/wic/canned-wks/stm32mp15x.wks.in
@@ -1,15 +1,13 @@
 #
-# Copyright (c) Siemens AG, 2020
+# Copyright (c) Siemens AG, 2020-2023
+# Copyright (c) 2021-2025 ilbers GmbH
 #
 # SPDX-License-Identifier: MIT
 
-part fsbl1 --part-name fsbl1 --source rawcopy --sourceparams "file=/usr/lib/trusted-firmware-a/${MACHINE}/tf-a-stm32mp157c-ev1.stm32" --fstype=ext4 --fsoptions "noauto" --part-type 0x8301 --fixed-size 256K
-part fsbl2 --part-name fsbl2 --source rawcopy --sourceparams "file=/usr/lib/trusted-firmware-a/${MACHINE}/tf-a-stm32mp157c-ev1.stm32" --fstype=ext4 --fsoptions "noauto" --part-type 0x8301 --fixed-size 256K
-part ssbl --part-name ssbl --source rawcopy --sourceparams "file=/usr/lib/u-boot/${MACHINE}/u-boot.stm32" --fstype=ext4 --fsoptions "noauto" --part-type 0x8301 --fixed-size 2048K
+part fsbl1 --source rawcopy --fstype=ext4 --part-name=fsbl1 --sourceparams "file=/usr/lib/trusted-firmware-a/${MACHINE}/tf-a-stm32mp157d-dk1.stm32" --ondisk mmcblk0 --part-type 0x8301 --fixed-size 256K --align 17
+part fsbl2 --source rawcopy --fstype=ext4 --part-name=fsbl2 --sourceparams "file=/usr/lib/trusted-firmware-a/${MACHINE}/tf-a-stm32mp157d-dk1.stm32" --ondisk mmcblk0 --part-type 0x8301 --fixed-size 256K
 
-part teeh --part-name teeh --source rawcopy --sourceparams "file=/usr/lib/optee-os/${MACHINE}/tee-header_v2.stm32" --fstype=ext4 --fsoptions "noauto" --part-type 0x8301 --fixed-size 256K
-part teed --part-name teed --source rawcopy --sourceparams "file=/usr/lib/optee-os/${MACHINE}/tee-pageable_v2.stm32" --fstype=ext4 --fsoptions "noauto" --part-type 0x8301 --fixed-size 1024K
-part teex --part-name teex --source rawcopy --sourceparams "file=/usr/lib/optee-os/${MACHINE}/tee-pager_v2.stm32" --fstype=ext4 --fsoptions "noauto" --part-type 0x8301 --fixed-size 256K
+part fip --source rawcopy --fstype=ext4 --part-name=fip --sourceparams="file=/usr/lib/trusted-firmware-a/${MACHINE}/fip.bin" --ondisk mmcblk0 --part-type 0xFFFF --fixed-size 4096K
 
 part / --source rootfs-u-boot --fstype ext4 --mkfs-extraopts "-T default" --label root --align 1024 --active --use-uuid
 
